xref: /openbmc/u-boot/include/fsl_pmic.h (revision 21299d3a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5  *
6  * (C) Copyright 2009 Freescale Semiconductor, Inc.
7  */
8 
9 #ifndef __FSL_PMIC_H__
10 #define __FSL_PMIC_H__
11 
12 /*
13  * The registers of different PMIC has the same meaning
14  * but the bit positions of the fields can differ or
15  * some fields has a meaning only on some devices.
16  * You have to check with the internal SPI bitmap
17  * (see Freescale Documentation) to set the registers
18  * for the device you are using
19  */
20 enum {
21 	REG_INT_STATUS0 = 0,
22 	REG_INT_MASK0,
23 	REG_INT_SENSE0,
24 	REG_INT_STATUS1,
25 	REG_INT_MASK1,
26 	REG_INT_SENSE1,
27 	REG_PU_MODE_S,
28 	REG_IDENTIFICATION,
29 	REG_UNUSED0,
30 	REG_ACC0,
31 	REG_ACC1,		/*10 */
32 	REG_UNUSED1,
33 	REG_UNUSED2,
34 	REG_POWER_CTL0,
35 	REG_POWER_CTL1,
36 	REG_POWER_CTL2,
37 	REG_REGEN_ASSIGN,
38 	REG_UNUSED3,
39 	REG_MEM_A,
40 	REG_MEM_B,
41 	REG_RTC_TIME,		/*20 */
42 	REG_RTC_ALARM,
43 	REG_RTC_DAY,
44 	REG_RTC_DAY_ALARM,
45 	REG_SW_0,
46 	REG_SW_1,
47 	REG_SW_2,
48 	REG_SW_3,
49 	REG_SW_4,
50 	REG_SW_5,
51 	REG_SETTING_0,		/*30 */
52 	REG_SETTING_1,
53 	REG_MODE_0,
54 	REG_MODE_1,
55 	REG_POWER_MISC,
56 	REG_UNUSED4,
57 	REG_UNUSED5,
58 	REG_UNUSED6,
59 	REG_UNUSED7,
60 	REG_UNUSED8,
61 	REG_UNUSED9,		/*40 */
62 	REG_UNUSED10,
63 	REG_UNUSED11,
64 	REG_ADC0,
65 	REG_ADC1,
66 	REG_ADC2,
67 	REG_ADC3,
68 	REG_ADC4,
69 	REG_CHARGE,
70 	REG_USB0,
71 	REG_USB1,		/*50 */
72 	REG_LED_CTL0,
73 	REG_LED_CTL1,
74 	REG_LED_CTL2,
75 	REG_LED_CTL3,
76 	REG_UNUSED12,
77 	REG_UNUSED13,
78 	REG_TRIM0,
79 	REG_TRIM1,
80 	REG_TEST0,
81 	REG_TEST1,		/*60 */
82 	REG_TEST2,
83 	REG_TEST3,
84 	REG_TEST4,
85 	PMIC_NUM_OF_REGS,
86 };
87 
88 /* REG_POWER_MISC */
89 #define GPO1EN		(1 << 6)
90 #define GPO1STBY	(1 << 7)
91 #define GPO2EN		(1 << 8)
92 #define GPO2STBY	(1 << 9)
93 #define GPO3EN		(1 << 10)
94 #define GPO3STBY	(1 << 11)
95 #define GPO4EN		(1 << 12)
96 #define GPO4STBY	(1 << 13)
97 #define PWGT1SPIEN	(1 << 15)
98 #define PWGT2SPIEN	(1 << 16)
99 #define PWUP		(1 << 21)
100 
101 /* Power Control 0 */
102 #define COINCHEN	(1 << 23)
103 #define BATTDETEN	(1 << 19)
104 
105 /* Interrupt status 1 */
106 #define RTCRSTI		(1 << 7)
107 
108 /* MC34708 Definitions */
109 #define SWx_VOLT_MASK_MC34708	0x3F
110 #define SWx_1_250V_MC34708	0x30
111 #define SWx_1_300V_MC34708	0x34
112 #define TIMER_MASK_MC34708	0x300
113 #define TIMER_4S_MC34708	0x100
114 #define VUSBSEL_MC34708		(1 << 2)
115 #define VUSBEN_MC34708		(1 << 3)
116 #define SWBST_CTRL		31
117 #define SWBST_AUTO		0x8
118 
119 #endif
120