1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 228bb6d34SStefano Babic /* 328bb6d34SStefano Babic * (C) Copyright 2010 428bb6d34SStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 528bb6d34SStefano Babic * 628bb6d34SStefano Babic * (C) Copyright 2009 Freescale Semiconductor, Inc. 728bb6d34SStefano Babic */ 828bb6d34SStefano Babic 928bb6d34SStefano Babic #ifndef __FSL_PMIC_H__ 1028bb6d34SStefano Babic #define __FSL_PMIC_H__ 1128bb6d34SStefano Babic 1228bb6d34SStefano Babic /* 1328bb6d34SStefano Babic * The registers of different PMIC has the same meaning 1428bb6d34SStefano Babic * but the bit positions of the fields can differ or 1528bb6d34SStefano Babic * some fields has a meaning only on some devices. 1628bb6d34SStefano Babic * You have to check with the internal SPI bitmap 1728bb6d34SStefano Babic * (see Freescale Documentation) to set the registers 1828bb6d34SStefano Babic * for the device you are using 1928bb6d34SStefano Babic */ 2028bb6d34SStefano Babic enum { 2128bb6d34SStefano Babic REG_INT_STATUS0 = 0, 2228bb6d34SStefano Babic REG_INT_MASK0, 2328bb6d34SStefano Babic REG_INT_SENSE0, 2428bb6d34SStefano Babic REG_INT_STATUS1, 2528bb6d34SStefano Babic REG_INT_MASK1, 2628bb6d34SStefano Babic REG_INT_SENSE1, 2728bb6d34SStefano Babic REG_PU_MODE_S, 2828bb6d34SStefano Babic REG_IDENTIFICATION, 2928bb6d34SStefano Babic REG_UNUSED0, 3028bb6d34SStefano Babic REG_ACC0, 3128bb6d34SStefano Babic REG_ACC1, /*10 */ 3228bb6d34SStefano Babic REG_UNUSED1, 3328bb6d34SStefano Babic REG_UNUSED2, 3428bb6d34SStefano Babic REG_POWER_CTL0, 3528bb6d34SStefano Babic REG_POWER_CTL1, 3628bb6d34SStefano Babic REG_POWER_CTL2, 3728bb6d34SStefano Babic REG_REGEN_ASSIGN, 3828bb6d34SStefano Babic REG_UNUSED3, 3928bb6d34SStefano Babic REG_MEM_A, 4028bb6d34SStefano Babic REG_MEM_B, 4128bb6d34SStefano Babic REG_RTC_TIME, /*20 */ 4228bb6d34SStefano Babic REG_RTC_ALARM, 4328bb6d34SStefano Babic REG_RTC_DAY, 4428bb6d34SStefano Babic REG_RTC_DAY_ALARM, 4528bb6d34SStefano Babic REG_SW_0, 4628bb6d34SStefano Babic REG_SW_1, 4728bb6d34SStefano Babic REG_SW_2, 4828bb6d34SStefano Babic REG_SW_3, 4928bb6d34SStefano Babic REG_SW_4, 5028bb6d34SStefano Babic REG_SW_5, 5128bb6d34SStefano Babic REG_SETTING_0, /*30 */ 5228bb6d34SStefano Babic REG_SETTING_1, 5328bb6d34SStefano Babic REG_MODE_0, 5428bb6d34SStefano Babic REG_MODE_1, 5528bb6d34SStefano Babic REG_POWER_MISC, 5628bb6d34SStefano Babic REG_UNUSED4, 5728bb6d34SStefano Babic REG_UNUSED5, 5828bb6d34SStefano Babic REG_UNUSED6, 5928bb6d34SStefano Babic REG_UNUSED7, 6028bb6d34SStefano Babic REG_UNUSED8, 6128bb6d34SStefano Babic REG_UNUSED9, /*40 */ 6228bb6d34SStefano Babic REG_UNUSED10, 6328bb6d34SStefano Babic REG_UNUSED11, 6428bb6d34SStefano Babic REG_ADC0, 6528bb6d34SStefano Babic REG_ADC1, 6628bb6d34SStefano Babic REG_ADC2, 6728bb6d34SStefano Babic REG_ADC3, 6828bb6d34SStefano Babic REG_ADC4, 6928bb6d34SStefano Babic REG_CHARGE, 7028bb6d34SStefano Babic REG_USB0, 7128bb6d34SStefano Babic REG_USB1, /*50 */ 7228bb6d34SStefano Babic REG_LED_CTL0, 7328bb6d34SStefano Babic REG_LED_CTL1, 7428bb6d34SStefano Babic REG_LED_CTL2, 7528bb6d34SStefano Babic REG_LED_CTL3, 7628bb6d34SStefano Babic REG_UNUSED12, 7728bb6d34SStefano Babic REG_UNUSED13, 7828bb6d34SStefano Babic REG_TRIM0, 7928bb6d34SStefano Babic REG_TRIM1, 8028bb6d34SStefano Babic REG_TEST0, 8128bb6d34SStefano Babic REG_TEST1, /*60 */ 8228bb6d34SStefano Babic REG_TEST2, 8328bb6d34SStefano Babic REG_TEST3, 8428bb6d34SStefano Babic REG_TEST4, 85b2e5add3SStefano Babic PMIC_NUM_OF_REGS, 8628bb6d34SStefano Babic }; 8728bb6d34SStefano Babic 8828bb6d34SStefano Babic /* REG_POWER_MISC */ 8928bb6d34SStefano Babic #define GPO1EN (1 << 6) 9028bb6d34SStefano Babic #define GPO1STBY (1 << 7) 9128bb6d34SStefano Babic #define GPO2EN (1 << 8) 9228bb6d34SStefano Babic #define GPO2STBY (1 << 9) 9328bb6d34SStefano Babic #define GPO3EN (1 << 10) 9428bb6d34SStefano Babic #define GPO3STBY (1 << 11) 9528bb6d34SStefano Babic #define GPO4EN (1 << 12) 9628bb6d34SStefano Babic #define GPO4STBY (1 << 13) 9728bb6d34SStefano Babic #define PWGT1SPIEN (1 << 15) 9828bb6d34SStefano Babic #define PWGT2SPIEN (1 << 16) 9928bb6d34SStefano Babic #define PWUP (1 << 21) 10028bb6d34SStefano Babic 10128bb6d34SStefano Babic /* Power Control 0 */ 10228bb6d34SStefano Babic #define COINCHEN (1 << 23) 10328bb6d34SStefano Babic #define BATTDETEN (1 << 19) 10428bb6d34SStefano Babic 10528bb6d34SStefano Babic /* Interrupt status 1 */ 10628bb6d34SStefano Babic #define RTCRSTI (1 << 7) 10728bb6d34SStefano Babic 1085b547f3cSFabio Estevam /* MC34708 Definitions */ 1095b547f3cSFabio Estevam #define SWx_VOLT_MASK_MC34708 0x3F 1105b547f3cSFabio Estevam #define SWx_1_250V_MC34708 0x30 1115b547f3cSFabio Estevam #define SWx_1_300V_MC34708 0x34 1125b547f3cSFabio Estevam #define TIMER_MASK_MC34708 0x300 1135b547f3cSFabio Estevam #define TIMER_4S_MC34708 0x100 1145b547f3cSFabio Estevam #define VUSBSEL_MC34708 (1 << 2) 1155b547f3cSFabio Estevam #define VUSBEN_MC34708 (1 << 3) 1165b547f3cSFabio Estevam #define SWBST_CTRL 31 117768a0597SFabio Estevam #define SWBST_AUTO 0x8 1185b547f3cSFabio Estevam 11928bb6d34SStefano Babic #endif 120