1*b7f2bbffSPrabhakar Kushwaha /* 2*b7f2bbffSPrabhakar Kushwaha * Copyright 2016 Freescale Semiconductor, Inc. 3*b7f2bbffSPrabhakar Kushwaha * 4*b7f2bbffSPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 5*b7f2bbffSPrabhakar Kushwaha */ 6*b7f2bbffSPrabhakar Kushwaha 7*b7f2bbffSPrabhakar Kushwaha #ifndef FSL_MMDC_H 8*b7f2bbffSPrabhakar Kushwaha #define FSL_MMDC_H 9*b7f2bbffSPrabhakar Kushwaha 10*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000 11*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954 12*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 13*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db 14*b7f2bbffSPrabhakar Kushwaha 15*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_MISC 0x00000680 16*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 17*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 18*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a 19*b7f2bbffSPrabhakar Kushwaha 20*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023 21*b7f2bbffSPrabhakar Kushwaha 22*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f 23*b7f2bbffSPrabhakar Kushwaha 24*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003 25*b7f2bbffSPrabhakar Kushwaha 26*b7f2bbffSPrabhakar Kushwaha #define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16) 27*b7f2bbffSPrabhakar Kushwaha 28*b7f2bbffSPrabhakar Kushwaha /* PHY Write Leveling Configuration and Error Status (MPWLGCR) */ 29*b7f2bbffSPrabhakar Kushwaha #define WR_LVL_HW_EN 0x00000001 30*b7f2bbffSPrabhakar Kushwaha 31*b7f2bbffSPrabhakar Kushwaha /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ 32*b7f2bbffSPrabhakar Kushwaha #define MPR_COMPARE_EN 0x00000001 33*b7f2bbffSPrabhakar Kushwaha 34*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040 35*b7f2bbffSPrabhakar Kushwaha 36*b7f2bbffSPrabhakar Kushwaha /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ 37*b7f2bbffSPrabhakar Kushwaha #define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000 38*b7f2bbffSPrabhakar Kushwaha 39*b7f2bbffSPrabhakar Kushwaha /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ 40*b7f2bbffSPrabhakar Kushwaha #define AUTO_RD_CALIBRATION_EN 0x00000010 41*b7f2bbffSPrabhakar Kushwaha 42*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035 43*b7f2bbffSPrabhakar Kushwaha 44*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067 45*b7f2bbffSPrabhakar Kushwaha 46*b7f2bbffSPrabhakar Kushwaha #define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000 47*b7f2bbffSPrabhakar Kushwaha 48*b7f2bbffSPrabhakar Kushwaha #define START_REFRESH 0x00000001 49*b7f2bbffSPrabhakar Kushwaha 50*b7f2bbffSPrabhakar Kushwaha /* MMDC Core Special Command Register (MDSCR) */ 51*b7f2bbffSPrabhakar Kushwaha #define CMD_ADDR_MSB_MR_OP(x) (x << 24) 52*b7f2bbffSPrabhakar Kushwaha 53*b7f2bbffSPrabhakar Kushwaha #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) 54*b7f2bbffSPrabhakar Kushwaha 55*b7f2bbffSPrabhakar Kushwaha #define DISABLE_CFG_REQ 0x0 56*b7f2bbffSPrabhakar Kushwaha #define CONFIGURATION_REQ (0x1 << 15) 57*b7f2bbffSPrabhakar Kushwaha #define WL_EN (0x1 << 9) 58*b7f2bbffSPrabhakar Kushwaha 59*b7f2bbffSPrabhakar Kushwaha #define CMD_NORMAL (0x0 << 4) 60*b7f2bbffSPrabhakar Kushwaha #define CMD_PRECHARGE (0x1 << 4) 61*b7f2bbffSPrabhakar Kushwaha #define CMD_AUTO_REFRESH (0x2 << 4) 62*b7f2bbffSPrabhakar Kushwaha #define CMD_LOAD_MODE_REG (0x3 << 4) 63*b7f2bbffSPrabhakar Kushwaha #define CMD_ZQ_CALIBRATION (0x4 << 4) 64*b7f2bbffSPrabhakar Kushwaha #define CMD_PRECHARGE_BANK_OPEN (0x5 << 4) 65*b7f2bbffSPrabhakar Kushwaha #define CMD_MRR (0x6 << 4) 66*b7f2bbffSPrabhakar Kushwaha 67*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_0 0x0 68*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_1 0x1 69*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_2 0x2 70*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_3 0x3 71*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_4 0x4 72*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_5 0x5 73*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_6 0x6 74*b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_7 0x7 75*b7f2bbffSPrabhakar Kushwaha 76*b7f2bbffSPrabhakar Kushwaha /* MMDC Registers */ 77*b7f2bbffSPrabhakar Kushwaha struct mmdc_p_regs { 78*b7f2bbffSPrabhakar Kushwaha u32 mdctl; 79*b7f2bbffSPrabhakar Kushwaha u32 mdpdc; 80*b7f2bbffSPrabhakar Kushwaha u32 mdotc; 81*b7f2bbffSPrabhakar Kushwaha u32 mdcfg0; 82*b7f2bbffSPrabhakar Kushwaha u32 mdcfg1; 83*b7f2bbffSPrabhakar Kushwaha u32 mdcfg2; 84*b7f2bbffSPrabhakar Kushwaha u32 mdmisc; 85*b7f2bbffSPrabhakar Kushwaha u32 mdscr; 86*b7f2bbffSPrabhakar Kushwaha u32 mdref; 87*b7f2bbffSPrabhakar Kushwaha u32 res1[2]; 88*b7f2bbffSPrabhakar Kushwaha u32 mdrwd; 89*b7f2bbffSPrabhakar Kushwaha u32 mdor; 90*b7f2bbffSPrabhakar Kushwaha u32 mdmrr; 91*b7f2bbffSPrabhakar Kushwaha u32 mdcfg3lp; 92*b7f2bbffSPrabhakar Kushwaha u32 mdmr4; 93*b7f2bbffSPrabhakar Kushwaha u32 mdasp; 94*b7f2bbffSPrabhakar Kushwaha u32 res2[239]; 95*b7f2bbffSPrabhakar Kushwaha u32 maarcr; 96*b7f2bbffSPrabhakar Kushwaha u32 mapsr; 97*b7f2bbffSPrabhakar Kushwaha u32 maexidr0; 98*b7f2bbffSPrabhakar Kushwaha u32 maexidr1; 99*b7f2bbffSPrabhakar Kushwaha u32 madpcr0; 100*b7f2bbffSPrabhakar Kushwaha u32 madpcr1; 101*b7f2bbffSPrabhakar Kushwaha u32 madpsr0; 102*b7f2bbffSPrabhakar Kushwaha u32 madpsr1; 103*b7f2bbffSPrabhakar Kushwaha u32 madpsr2; 104*b7f2bbffSPrabhakar Kushwaha u32 madpsr3; 105*b7f2bbffSPrabhakar Kushwaha u32 madpsr4; 106*b7f2bbffSPrabhakar Kushwaha u32 madpsr5; 107*b7f2bbffSPrabhakar Kushwaha u32 masbs0; 108*b7f2bbffSPrabhakar Kushwaha u32 masbs1; 109*b7f2bbffSPrabhakar Kushwaha u32 res3[2]; 110*b7f2bbffSPrabhakar Kushwaha u32 magenp; 111*b7f2bbffSPrabhakar Kushwaha u32 res4[239]; 112*b7f2bbffSPrabhakar Kushwaha u32 mpzqhwctrl; 113*b7f2bbffSPrabhakar Kushwaha u32 mpzqswctrl; 114*b7f2bbffSPrabhakar Kushwaha u32 mpwlgcr; 115*b7f2bbffSPrabhakar Kushwaha u32 mpwldectrl0; 116*b7f2bbffSPrabhakar Kushwaha u32 mpwldectrl1; 117*b7f2bbffSPrabhakar Kushwaha u32 mpwldlst; 118*b7f2bbffSPrabhakar Kushwaha u32 mpodtctrl; 119*b7f2bbffSPrabhakar Kushwaha u32 mprddqby0dl; 120*b7f2bbffSPrabhakar Kushwaha u32 mprddqby1dl; 121*b7f2bbffSPrabhakar Kushwaha u32 mprddqby2dl; 122*b7f2bbffSPrabhakar Kushwaha u32 mprddqby3dl; 123*b7f2bbffSPrabhakar Kushwaha u32 res5[4]; 124*b7f2bbffSPrabhakar Kushwaha u32 mpdgctrl0; 125*b7f2bbffSPrabhakar Kushwaha u32 mpdgctrl1; 126*b7f2bbffSPrabhakar Kushwaha u32 mpdgdlst0; 127*b7f2bbffSPrabhakar Kushwaha u32 mprddlctl; 128*b7f2bbffSPrabhakar Kushwaha u32 mprddlst; 129*b7f2bbffSPrabhakar Kushwaha u32 mpwrdlctl; 130*b7f2bbffSPrabhakar Kushwaha u32 mpwrdlst; 131*b7f2bbffSPrabhakar Kushwaha u32 mpsdctrl; 132*b7f2bbffSPrabhakar Kushwaha u32 mpzqlp2ctl; 133*b7f2bbffSPrabhakar Kushwaha u32 mprddlhwctl; 134*b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwctl; 135*b7f2bbffSPrabhakar Kushwaha u32 mprddlhwst0; 136*b7f2bbffSPrabhakar Kushwaha u32 mprddlhwst1; 137*b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwst0; 138*b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwst1; 139*b7f2bbffSPrabhakar Kushwaha u32 mpwlhwerr; 140*b7f2bbffSPrabhakar Kushwaha u32 mpdghwst0; 141*b7f2bbffSPrabhakar Kushwaha u32 mpdghwst1; 142*b7f2bbffSPrabhakar Kushwaha u32 mpdghwst2; 143*b7f2bbffSPrabhakar Kushwaha u32 mpdghwst3; 144*b7f2bbffSPrabhakar Kushwaha u32 mppdcmpr1; 145*b7f2bbffSPrabhakar Kushwaha u32 mppdcmpr2; 146*b7f2bbffSPrabhakar Kushwaha u32 mpswdar0; 147*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr0; 148*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr1; 149*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr2; 150*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr3; 151*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr4; 152*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr5; 153*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr6; 154*b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr7; 155*b7f2bbffSPrabhakar Kushwaha u32 mpmur0; 156*b7f2bbffSPrabhakar Kushwaha u32 mpwrcadl; 157*b7f2bbffSPrabhakar Kushwaha u32 mpdccr; 158*b7f2bbffSPrabhakar Kushwaha }; 159*b7f2bbffSPrabhakar Kushwaha 160*b7f2bbffSPrabhakar Kushwaha #endif /* FSL_MMDC_H */ 161