1b7f2bbffSPrabhakar Kushwaha /* 2b7f2bbffSPrabhakar Kushwaha * Copyright 2016 Freescale Semiconductor, Inc. 3b7f2bbffSPrabhakar Kushwaha * 4b7f2bbffSPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 5b7f2bbffSPrabhakar Kushwaha */ 6b7f2bbffSPrabhakar Kushwaha 7b7f2bbffSPrabhakar Kushwaha #ifndef FSL_MMDC_H 8b7f2bbffSPrabhakar Kushwaha #define FSL_MMDC_H 9b7f2bbffSPrabhakar Kushwaha 10b9e745bbSShengzhou Liu /* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */ 11b9e745bbSShengzhou Liu #define MPWLGCR_HW_WL_EN (1 << 0) 12b7f2bbffSPrabhakar Kushwaha 13b7f2bbffSPrabhakar Kushwaha /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */ 14b9e745bbSShengzhou Liu #define MPPDCMPR2_MPR_COMPARE_EN (1 << 0) 15b7f2bbffSPrabhakar Kushwaha 16b7f2bbffSPrabhakar Kushwaha 17b7f2bbffSPrabhakar Kushwaha /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */ 18b9e745bbSShengzhou Liu #define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28) 19b7f2bbffSPrabhakar Kushwaha 20b7f2bbffSPrabhakar Kushwaha /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */ 21b9e745bbSShengzhou Liu #define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4) 22b7f2bbffSPrabhakar Kushwaha 23b9e745bbSShengzhou Liu /* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */ 24b9e745bbSShengzhou Liu #define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067 25b7f2bbffSPrabhakar Kushwaha 26b9e745bbSShengzhou Liu /* MMDC Core Refresh Control Register (MMDC_MDREF) */ 27b9e745bbSShengzhou Liu #define MDREF_START_REFRESH (1 << 0) 28b7f2bbffSPrabhakar Kushwaha 29b7f2bbffSPrabhakar Kushwaha /* MMDC Core Special Command Register (MDSCR) */ 30b7f2bbffSPrabhakar Kushwaha #define CMD_ADDR_MSB_MR_OP(x) (x << 24) 31b7f2bbffSPrabhakar Kushwaha #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16) 32b9e745bbSShengzhou Liu #define MDSCR_DISABLE_CFG_REQ (0 << 15) 33b9e745bbSShengzhou Liu #define MDSCR_ENABLE_CON_REQ (1 << 15) 34b9e745bbSShengzhou Liu #define MDSCR_CON_ACK (1 << 14) 35b9e745bbSShengzhou Liu #define MDSCR_WL_EN (1 << 9) 36b9e745bbSShengzhou Liu #define CMD_NORMAL (0 << 4) 37b9e745bbSShengzhou Liu #define CMD_PRECHARGE (1 << 4) 38b9e745bbSShengzhou Liu #define CMD_AUTO_REFRESH (2 << 4) 39b9e745bbSShengzhou Liu #define CMD_LOAD_MODE_REG (3 << 4) 40b9e745bbSShengzhou Liu #define CMD_ZQ_CALIBRATION (4 << 4) 41b9e745bbSShengzhou Liu #define CMD_PRECHARGE_BANK_OPEN (5 << 4) 42b9e745bbSShengzhou Liu #define CMD_MRR (6 << 4) 43b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_0 0x0 44b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_1 0x1 45b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_2 0x2 46b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_3 0x3 47b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_4 0x4 48b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_5 0x5 49b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_6 0x6 50b7f2bbffSPrabhakar Kushwaha #define CMD_BANK_ADDR_7 0x7 51b7f2bbffSPrabhakar Kushwaha 52b9e745bbSShengzhou Liu /* MMDC Core Control Register (MDCTL) */ 53b9e745bbSShengzhou Liu #define MDCTL_SDE0 (1 << 31) 54b9e745bbSShengzhou Liu #define MDCTL_SDE1 (1 << 30) 55b9e745bbSShengzhou Liu 56b9e745bbSShengzhou Liu /* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */ 57b9e745bbSShengzhou Liu #define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16) 58b9e745bbSShengzhou Liu 59b9e745bbSShengzhou Liu /* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */ 60b9e745bbSShengzhou Liu #define MMDC_MPMUR0_FRC_MSR (1 << 11) 61b9e745bbSShengzhou Liu 62b9e745bbSShengzhou Liu /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */ 63b9e745bbSShengzhou Liu /* default 64 for a quarter cycle delay */ 64b9e745bbSShengzhou Liu #define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040 65b9e745bbSShengzhou Liu 66b7f2bbffSPrabhakar Kushwaha /* MMDC Registers */ 67b9e745bbSShengzhou Liu struct mmdc_regs { 68b7f2bbffSPrabhakar Kushwaha u32 mdctl; 69b7f2bbffSPrabhakar Kushwaha u32 mdpdc; 70b7f2bbffSPrabhakar Kushwaha u32 mdotc; 71b7f2bbffSPrabhakar Kushwaha u32 mdcfg0; 72b7f2bbffSPrabhakar Kushwaha u32 mdcfg1; 73b7f2bbffSPrabhakar Kushwaha u32 mdcfg2; 74b7f2bbffSPrabhakar Kushwaha u32 mdmisc; 75b7f2bbffSPrabhakar Kushwaha u32 mdscr; 76b7f2bbffSPrabhakar Kushwaha u32 mdref; 77b7f2bbffSPrabhakar Kushwaha u32 res1[2]; 78b7f2bbffSPrabhakar Kushwaha u32 mdrwd; 79b7f2bbffSPrabhakar Kushwaha u32 mdor; 80b7f2bbffSPrabhakar Kushwaha u32 mdmrr; 81b7f2bbffSPrabhakar Kushwaha u32 mdcfg3lp; 82b7f2bbffSPrabhakar Kushwaha u32 mdmr4; 83b7f2bbffSPrabhakar Kushwaha u32 mdasp; 84b7f2bbffSPrabhakar Kushwaha u32 res2[239]; 85b7f2bbffSPrabhakar Kushwaha u32 maarcr; 86b7f2bbffSPrabhakar Kushwaha u32 mapsr; 87b7f2bbffSPrabhakar Kushwaha u32 maexidr0; 88b7f2bbffSPrabhakar Kushwaha u32 maexidr1; 89b7f2bbffSPrabhakar Kushwaha u32 madpcr0; 90b7f2bbffSPrabhakar Kushwaha u32 madpcr1; 91b7f2bbffSPrabhakar Kushwaha u32 madpsr0; 92b7f2bbffSPrabhakar Kushwaha u32 madpsr1; 93b7f2bbffSPrabhakar Kushwaha u32 madpsr2; 94b7f2bbffSPrabhakar Kushwaha u32 madpsr3; 95b7f2bbffSPrabhakar Kushwaha u32 madpsr4; 96b7f2bbffSPrabhakar Kushwaha u32 madpsr5; 97b7f2bbffSPrabhakar Kushwaha u32 masbs0; 98b7f2bbffSPrabhakar Kushwaha u32 masbs1; 99b7f2bbffSPrabhakar Kushwaha u32 res3[2]; 100b7f2bbffSPrabhakar Kushwaha u32 magenp; 101b7f2bbffSPrabhakar Kushwaha u32 res4[239]; 102b7f2bbffSPrabhakar Kushwaha u32 mpzqhwctrl; 103b7f2bbffSPrabhakar Kushwaha u32 mpzqswctrl; 104b7f2bbffSPrabhakar Kushwaha u32 mpwlgcr; 105b7f2bbffSPrabhakar Kushwaha u32 mpwldectrl0; 106b7f2bbffSPrabhakar Kushwaha u32 mpwldectrl1; 107b7f2bbffSPrabhakar Kushwaha u32 mpwldlst; 108b7f2bbffSPrabhakar Kushwaha u32 mpodtctrl; 109b7f2bbffSPrabhakar Kushwaha u32 mprddqby0dl; 110b7f2bbffSPrabhakar Kushwaha u32 mprddqby1dl; 111b7f2bbffSPrabhakar Kushwaha u32 mprddqby2dl; 112b7f2bbffSPrabhakar Kushwaha u32 mprddqby3dl; 113b9e745bbSShengzhou Liu u32 mpwrdqby0dl; 114b9e745bbSShengzhou Liu u32 mpwrdqby1dl; 115b9e745bbSShengzhou Liu u32 mpwrdqby2dl; 116b9e745bbSShengzhou Liu u32 mpwrdqby3dl; 117b7f2bbffSPrabhakar Kushwaha u32 mpdgctrl0; 118b7f2bbffSPrabhakar Kushwaha u32 mpdgctrl1; 119b7f2bbffSPrabhakar Kushwaha u32 mpdgdlst0; 120b7f2bbffSPrabhakar Kushwaha u32 mprddlctl; 121b7f2bbffSPrabhakar Kushwaha u32 mprddlst; 122b7f2bbffSPrabhakar Kushwaha u32 mpwrdlctl; 123b7f2bbffSPrabhakar Kushwaha u32 mpwrdlst; 124b7f2bbffSPrabhakar Kushwaha u32 mpsdctrl; 125b7f2bbffSPrabhakar Kushwaha u32 mpzqlp2ctl; 126b7f2bbffSPrabhakar Kushwaha u32 mprddlhwctl; 127b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwctl; 128b7f2bbffSPrabhakar Kushwaha u32 mprddlhwst0; 129b7f2bbffSPrabhakar Kushwaha u32 mprddlhwst1; 130b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwst0; 131b7f2bbffSPrabhakar Kushwaha u32 mpwrdlhwst1; 132b7f2bbffSPrabhakar Kushwaha u32 mpwlhwerr; 133b7f2bbffSPrabhakar Kushwaha u32 mpdghwst0; 134b7f2bbffSPrabhakar Kushwaha u32 mpdghwst1; 135b7f2bbffSPrabhakar Kushwaha u32 mpdghwst2; 136b7f2bbffSPrabhakar Kushwaha u32 mpdghwst3; 137b7f2bbffSPrabhakar Kushwaha u32 mppdcmpr1; 138b7f2bbffSPrabhakar Kushwaha u32 mppdcmpr2; 139b7f2bbffSPrabhakar Kushwaha u32 mpswdar0; 140b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr0; 141b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr1; 142b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr2; 143b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr3; 144b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr4; 145b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr5; 146b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr6; 147b7f2bbffSPrabhakar Kushwaha u32 mpswdrdr7; 148b7f2bbffSPrabhakar Kushwaha u32 mpmur0; 149b7f2bbffSPrabhakar Kushwaha u32 mpwrcadl; 150b7f2bbffSPrabhakar Kushwaha u32 mpdccr; 151b7f2bbffSPrabhakar Kushwaha }; 152b7f2bbffSPrabhakar Kushwaha 153*1fdcc8dfSYork Sun struct fsl_mmdc_info { 154*1fdcc8dfSYork Sun u32 mdctl; 155*1fdcc8dfSYork Sun u32 mdpdc; 156*1fdcc8dfSYork Sun u32 mdotc; 157*1fdcc8dfSYork Sun u32 mdcfg0; 158*1fdcc8dfSYork Sun u32 mdcfg1; 159*1fdcc8dfSYork Sun u32 mdcfg2; 160*1fdcc8dfSYork Sun u32 mdmisc; 161*1fdcc8dfSYork Sun u32 mdref; 162*1fdcc8dfSYork Sun u32 mdrwd; 163*1fdcc8dfSYork Sun u32 mdor; 164*1fdcc8dfSYork Sun u32 mdasp; 165*1fdcc8dfSYork Sun u32 mpodtctrl; 166*1fdcc8dfSYork Sun u32 mpzqhwctrl; 167*1fdcc8dfSYork Sun u32 mprddlctl; 168*1fdcc8dfSYork Sun }; 169b9e745bbSShengzhou Liu 170*1fdcc8dfSYork Sun void mmdc_init(const struct fsl_mmdc_info *); 171b9e745bbSShengzhou Liu 172b7f2bbffSPrabhakar Kushwaha #endif /* FSL_MMDC_H */ 173