19a17eb5bSYork Sun /* 29a17eb5bSYork Sun * Common internal memory map for some Freescale SoCs 39a17eb5bSYork Sun * 434e026f9SYork Sun * Copyright 2013-2014 Freescale Semiconductor, Inc. 59a17eb5bSYork Sun * 69a17eb5bSYork Sun * SPDX-License-Identifier: GPL-2.0+ 79a17eb5bSYork Sun */ 89a17eb5bSYork Sun 99a17eb5bSYork Sun #ifndef __FSL_IMMAP_H 109a17eb5bSYork Sun #define __FSL_IMMAP_H 119a17eb5bSYork Sun /* 129a17eb5bSYork Sun * DDR memory controller registers 139a17eb5bSYork Sun * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. 149a17eb5bSYork Sun */ 159a17eb5bSYork Sun struct ccsr_ddr { 169a17eb5bSYork Sun u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 179a17eb5bSYork Sun u8 res_04[4]; 189a17eb5bSYork Sun u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 199a17eb5bSYork Sun u8 res_0c[4]; 209a17eb5bSYork Sun u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 219a17eb5bSYork Sun u8 res_14[4]; 229a17eb5bSYork Sun u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 239a17eb5bSYork Sun u8 res_1c[100]; 249a17eb5bSYork Sun u32 cs0_config; /* Chip Select Configuration */ 259a17eb5bSYork Sun u32 cs1_config; /* Chip Select Configuration */ 269a17eb5bSYork Sun u32 cs2_config; /* Chip Select Configuration */ 279a17eb5bSYork Sun u32 cs3_config; /* Chip Select Configuration */ 289a17eb5bSYork Sun u8 res_90[48]; 299a17eb5bSYork Sun u32 cs0_config_2; /* Chip Select Configuration 2 */ 309a17eb5bSYork Sun u32 cs1_config_2; /* Chip Select Configuration 2 */ 319a17eb5bSYork Sun u32 cs2_config_2; /* Chip Select Configuration 2 */ 329a17eb5bSYork Sun u32 cs3_config_2; /* Chip Select Configuration 2 */ 339a17eb5bSYork Sun u8 res_d0[48]; 349a17eb5bSYork Sun u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 359a17eb5bSYork Sun u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 369a17eb5bSYork Sun u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 379a17eb5bSYork Sun u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 389a17eb5bSYork Sun u32 sdram_cfg; /* SDRAM Control Configuration */ 399a17eb5bSYork Sun u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 409a17eb5bSYork Sun u32 sdram_mode; /* SDRAM Mode Configuration */ 419a17eb5bSYork Sun u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 429a17eb5bSYork Sun u32 sdram_md_cntl; /* SDRAM Mode Control */ 439a17eb5bSYork Sun u32 sdram_interval; /* SDRAM Interval Configuration */ 449a17eb5bSYork Sun u32 sdram_data_init; /* SDRAM Data initialization */ 459a17eb5bSYork Sun u8 res_12c[4]; 469a17eb5bSYork Sun u32 sdram_clk_cntl; /* SDRAM Clock Control */ 479a17eb5bSYork Sun u8 res_134[20]; 489a17eb5bSYork Sun u32 init_addr; /* training init addr */ 499a17eb5bSYork Sun u32 init_ext_addr; /* training init extended addr */ 509a17eb5bSYork Sun u8 res_150[16]; 519a17eb5bSYork Sun u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 529a17eb5bSYork Sun u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 5334e026f9SYork Sun u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ 5434e026f9SYork Sun u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ 559a17eb5bSYork Sun u32 ddr_zq_cntl; /* ZQ calibration control*/ 569a17eb5bSYork Sun u32 ddr_wrlvl_cntl; /* write leveling control*/ 579a17eb5bSYork Sun u8 reg_178[4]; 589a17eb5bSYork Sun u32 ddr_sr_cntr; /* self refresh counter */ 599a17eb5bSYork Sun u32 ddr_sdram_rcw_1; /* Control Words 1 */ 609a17eb5bSYork Sun u32 ddr_sdram_rcw_2; /* Control Words 2 */ 619a17eb5bSYork Sun u8 reg_188[8]; 629a17eb5bSYork Sun u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 639a17eb5bSYork Sun u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 6434e026f9SYork Sun u8 res_198[0x1a0-0x198]; 6534e026f9SYork Sun u32 ddr_sdram_rcw_3; 6634e026f9SYork Sun u32 ddr_sdram_rcw_4; 6734e026f9SYork Sun u32 ddr_sdram_rcw_5; 6834e026f9SYork Sun u32 ddr_sdram_rcw_6; 6934e026f9SYork Sun u8 res_1b0[0x200-0x1b0]; 709a17eb5bSYork Sun u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 719a17eb5bSYork Sun u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 729a17eb5bSYork Sun u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 739a17eb5bSYork Sun u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 749a17eb5bSYork Sun u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 759a17eb5bSYork Sun u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 7634e026f9SYork Sun u8 res_218[0x220-0x218]; 7734e026f9SYork Sun u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ 7834e026f9SYork Sun u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ 7934e026f9SYork Sun u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ 8034e026f9SYork Sun u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ 8134e026f9SYork Sun u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ 8234e026f9SYork Sun u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ 8334e026f9SYork Sun u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ 8434e026f9SYork Sun u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ 8534e026f9SYork Sun u8 res_240[0x250-0x240]; 8634e026f9SYork Sun u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ 8734e026f9SYork Sun u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ 8834e026f9SYork Sun u8 res_258[0x260-0x258]; 8934e026f9SYork Sun u32 sdram_cfg_3; 90d9be24c9SYork Sun u8 res_264[0x400-0x264]; 9134e026f9SYork Sun u32 dq_map_0; 9234e026f9SYork Sun u32 dq_map_1; 9334e026f9SYork Sun u32 dq_map_2; 9434e026f9SYork Sun u32 dq_map_3; 9534e026f9SYork Sun u8 res_410[0xb20-0x410]; 969a17eb5bSYork Sun u32 ddr_dsr1; /* Debug Status 1 */ 979a17eb5bSYork Sun u32 ddr_dsr2; /* Debug Status 2 */ 989a17eb5bSYork Sun u32 ddr_cdr1; /* Control Driver 1 */ 999a17eb5bSYork Sun u32 ddr_cdr2; /* Control Driver 2 */ 1009a17eb5bSYork Sun u8 res_b30[200]; 1019a17eb5bSYork Sun u32 ip_rev1; /* IP Block Revision 1 */ 1029a17eb5bSYork Sun u32 ip_rev2; /* IP Block Revision 2 */ 1039a17eb5bSYork Sun u32 eor; /* Enhanced Optimization Register */ 1049a17eb5bSYork Sun u8 res_c04[252]; 1059a17eb5bSYork Sun u32 mtcr; /* Memory Test Control Register */ 1069a17eb5bSYork Sun u8 res_d04[28]; 1079a17eb5bSYork Sun u32 mtp1; /* Memory Test Pattern 1 */ 1089a17eb5bSYork Sun u32 mtp2; /* Memory Test Pattern 2 */ 1099a17eb5bSYork Sun u32 mtp3; /* Memory Test Pattern 3 */ 1109a17eb5bSYork Sun u32 mtp4; /* Memory Test Pattern 4 */ 1119a17eb5bSYork Sun u32 mtp5; /* Memory Test Pattern 5 */ 1129a17eb5bSYork Sun u32 mtp6; /* Memory Test Pattern 6 */ 1139a17eb5bSYork Sun u32 mtp7; /* Memory Test Pattern 7 */ 1149a17eb5bSYork Sun u32 mtp8; /* Memory Test Pattern 8 */ 1159a17eb5bSYork Sun u32 mtp9; /* Memory Test Pattern 9 */ 1169a17eb5bSYork Sun u32 mtp10; /* Memory Test Pattern 10 */ 1179a17eb5bSYork Sun u8 res_d48[184]; 1189a17eb5bSYork Sun u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 1199a17eb5bSYork Sun u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 1209a17eb5bSYork Sun u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 1219a17eb5bSYork Sun u8 res_e0c[20]; 1229a17eb5bSYork Sun u32 capture_data_hi; /* Data Path Read Capture High */ 1239a17eb5bSYork Sun u32 capture_data_lo; /* Data Path Read Capture Low */ 1249a17eb5bSYork Sun u32 capture_ecc; /* Data Path Read Capture ECC */ 1259a17eb5bSYork Sun u8 res_e2c[20]; 1269a17eb5bSYork Sun u32 err_detect; /* Error Detect */ 1279a17eb5bSYork Sun u32 err_disable; /* Error Disable */ 1289a17eb5bSYork Sun u32 err_int_en; 1299a17eb5bSYork Sun u32 capture_attributes; /* Error Attrs Capture */ 1309a17eb5bSYork Sun u32 capture_address; /* Error Addr Capture */ 1319a17eb5bSYork Sun u32 capture_ext_address; /* Error Extended Addr Capture */ 1329a17eb5bSYork Sun u32 err_sbe; /* Single-Bit ECC Error Management */ 1339a17eb5bSYork Sun u8 res_e5c[164]; 134b406731aSYork Sun u32 debug[64]; /* debug_1 to debug_64 */ 1359a17eb5bSYork Sun }; 136*63b2316cSAshish Kumar 137*63b2316cSAshish Kumar #ifdef CONFIG_SYS_FSL_HAS_CCI400 138*63b2316cSAshish Kumar #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 139*63b2316cSAshish Kumar #define CCI400_CTRLORD_EN_BARRIER 0 140*63b2316cSAshish Kumar #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 141*63b2316cSAshish Kumar #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 142*63b2316cSAshish Kumar #define CCI400_SNOOP_REQ_EN 0x00000001 143*63b2316cSAshish Kumar 144*63b2316cSAshish Kumar /* CCI-400 registers */ 145*63b2316cSAshish Kumar struct ccsr_cci400 { 146*63b2316cSAshish Kumar u32 ctrl_ord; /* Control Override */ 147*63b2316cSAshish Kumar u32 spec_ctrl; /* Speculation Control */ 148*63b2316cSAshish Kumar u32 secure_access; /* Secure Access */ 149*63b2316cSAshish Kumar u32 status; /* Status */ 150*63b2316cSAshish Kumar u32 impr_err; /* Imprecise Error */ 151*63b2316cSAshish Kumar u8 res_14[0x100 - 0x14]; 152*63b2316cSAshish Kumar u32 pmcr; /* Performance Monitor Control */ 153*63b2316cSAshish Kumar u8 res_104[0xfd0 - 0x104]; 154*63b2316cSAshish Kumar u32 pid[8]; /* Peripheral ID */ 155*63b2316cSAshish Kumar u32 cid[4]; /* Component ID */ 156*63b2316cSAshish Kumar struct { 157*63b2316cSAshish Kumar u32 snoop_ctrl; /* Snoop Control */ 158*63b2316cSAshish Kumar u32 sha_ord; /* Shareable Override */ 159*63b2316cSAshish Kumar u8 res_1008[0x1100 - 0x1008]; 160*63b2316cSAshish Kumar u32 rc_qos_ord; /* read channel QoS Value Override */ 161*63b2316cSAshish Kumar u32 wc_qos_ord; /* read channel QoS Value Override */ 162*63b2316cSAshish Kumar u8 res_1108[0x110c - 0x1108]; 163*63b2316cSAshish Kumar u32 qos_ctrl; /* QoS Control */ 164*63b2316cSAshish Kumar u32 max_ot; /* Max OT */ 165*63b2316cSAshish Kumar u8 res_1114[0x1130 - 0x1114]; 166*63b2316cSAshish Kumar u32 target_lat; /* Target Latency */ 167*63b2316cSAshish Kumar u32 latency_regu; /* Latency Regulation */ 168*63b2316cSAshish Kumar u32 qos_range; /* QoS Range */ 169*63b2316cSAshish Kumar u8 res_113c[0x2000 - 0x113c]; 170*63b2316cSAshish Kumar } slave[5]; /* Slave Interface */ 171*63b2316cSAshish Kumar u8 res_6000[0x9004 - 0x6000]; 172*63b2316cSAshish Kumar u32 cycle_counter; /* Cycle counter */ 173*63b2316cSAshish Kumar u32 count_ctrl; /* Count Control */ 174*63b2316cSAshish Kumar u32 overflow_status; /* Overflow Flag Status */ 175*63b2316cSAshish Kumar u8 res_9010[0xa000 - 0x9010]; 176*63b2316cSAshish Kumar struct { 177*63b2316cSAshish Kumar u32 event_select; /* Event Select */ 178*63b2316cSAshish Kumar u32 event_count; /* Event Count */ 179*63b2316cSAshish Kumar u32 counter_ctrl; /* Counter Control */ 180*63b2316cSAshish Kumar u32 overflow_status; /* Overflow Flag Status */ 181*63b2316cSAshish Kumar u8 res_a010[0xb000 - 0xa010]; 182*63b2316cSAshish Kumar } pcounter[4]; /* Performance Counter */ 183*63b2316cSAshish Kumar u8 res_e004[0x10000 - 0xe004]; 184*63b2316cSAshish Kumar }; 185*63b2316cSAshish Kumar #endif 186*63b2316cSAshish Kumar 1879a17eb5bSYork Sun #endif /* __FSL_IMMAP_H */ 188