1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __FSL_IFC_H 9 #define __FSL_IFC_H 10 11 #ifdef CONFIG_FSL_IFC 12 #include <config.h> 13 #include <common.h> 14 15 #define FSL_IFC_V1_1_0 0x01010000 16 #define FSL_IFC_V2_0_0 0x02000000 17 18 #ifdef CONFIG_SYS_FSL_IFC_LE 19 #define ifc_in32(a) in_le32(a) 20 #define ifc_out32(a, v) out_le32(a, v) 21 #define ifc_in16(a) in_le16(a) 22 #define ifc_out16(a, v) out_le16(a, v) 23 #elif defined(CONFIG_SYS_FSL_IFC_BE) 24 #define ifc_in32(a) in_be32(a) 25 #define ifc_out32(a, v) out_be32(a, v) 26 #define ifc_in16(a) in_be16(a) 27 #define ifc_out16(a, v) out_be16(a, v) 28 #else 29 #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined 30 #endif 31 32 33 /* 34 * CSPR - Chip Select Property Register 35 */ 36 #define CSPR_BA 0xFFFF0000 37 #define CSPR_BA_SHIFT 16 38 #define CSPR_PORT_SIZE 0x00000180 39 #define CSPR_PORT_SIZE_SHIFT 7 40 /* Port Size 8 bit */ 41 #define CSPR_PORT_SIZE_8 0x00000080 42 /* Port Size 16 bit */ 43 #define CSPR_PORT_SIZE_16 0x00000100 44 /* Port Size 32 bit */ 45 #define CSPR_PORT_SIZE_32 0x00000180 46 /* Write Protect */ 47 #define CSPR_WP 0x00000040 48 #define CSPR_WP_SHIFT 6 49 /* Machine Select */ 50 #define CSPR_MSEL 0x00000006 51 #define CSPR_MSEL_SHIFT 1 52 /* NOR */ 53 #define CSPR_MSEL_NOR 0x00000000 54 /* NAND */ 55 #define CSPR_MSEL_NAND 0x00000002 56 /* GPCM */ 57 #define CSPR_MSEL_GPCM 0x00000004 58 /* Bank Valid */ 59 #define CSPR_V 0x00000001 60 #define CSPR_V_SHIFT 0 61 62 /* Convert an address into the right format for the CSPR Registers */ 63 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) 64 65 /* 66 * Address Mask Register 67 */ 68 #define IFC_AMASK_MASK 0xFFFF0000 69 #define IFC_AMASK_SHIFT 16 70 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 71 (__ilog2(n) - IFC_AMASK_SHIFT)) 72 73 /* 74 * Chip Select Option Register IFC_NAND Machine 75 */ 76 /* Enable ECC Encoder */ 77 #define CSOR_NAND_ECC_ENC_EN 0x80000000 78 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 79 /* 4 bit correction per 520 Byte sector */ 80 #define CSOR_NAND_ECC_MODE_4 0x00000000 81 /* 8 bit correction per 528 Byte sector */ 82 #define CSOR_NAND_ECC_MODE_8 0x10000000 83 /* Enable ECC Decoder */ 84 #define CSOR_NAND_ECC_DEC_EN 0x04000000 85 /* Row Address Length */ 86 #define CSOR_NAND_RAL_MASK 0x01800000 87 #define CSOR_NAND_RAL_SHIFT 20 88 #define CSOR_NAND_RAL_1 0x00000000 89 #define CSOR_NAND_RAL_2 0x00800000 90 #define CSOR_NAND_RAL_3 0x01000000 91 #define CSOR_NAND_RAL_4 0x01800000 92 /* Page Size 512b, 2k, 4k */ 93 #define CSOR_NAND_PGS_MASK 0x00180000 94 #define CSOR_NAND_PGS_SHIFT 16 95 #define CSOR_NAND_PGS_512 0x00000000 96 #define CSOR_NAND_PGS_2K 0x00080000 97 #define CSOR_NAND_PGS_4K 0x00100000 98 #define CSOR_NAND_PGS_8K 0x00180000 99 /* Spare region Size */ 100 #define CSOR_NAND_SPRZ_MASK 0x0000E000 101 #define CSOR_NAND_SPRZ_SHIFT 13 102 #define CSOR_NAND_SPRZ_16 0x00000000 103 #define CSOR_NAND_SPRZ_64 0x00002000 104 #define CSOR_NAND_SPRZ_128 0x00004000 105 #define CSOR_NAND_SPRZ_210 0x00006000 106 #define CSOR_NAND_SPRZ_218 0x00008000 107 #define CSOR_NAND_SPRZ_224 0x0000A000 108 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 109 /* Pages Per Block */ 110 #define CSOR_NAND_PB_MASK 0x00000700 111 #define CSOR_NAND_PB_SHIFT 8 112 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) 113 /* Time for Read Enable High to Output High Impedance */ 114 #define CSOR_NAND_TRHZ_MASK 0x0000001C 115 #define CSOR_NAND_TRHZ_SHIFT 2 116 #define CSOR_NAND_TRHZ_20 0x00000000 117 #define CSOR_NAND_TRHZ_40 0x00000004 118 #define CSOR_NAND_TRHZ_60 0x00000008 119 #define CSOR_NAND_TRHZ_80 0x0000000C 120 #define CSOR_NAND_TRHZ_100 0x00000010 121 /* Buffer control disable */ 122 #define CSOR_NAND_BCTLD 0x00000001 123 124 /* 125 * Chip Select Option Register - NOR Flash Mode 126 */ 127 /* Enable Address shift Mode */ 128 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 129 /* Page Read Enable from NOR device */ 130 #define CSOR_NOR_PGRD_EN 0x10000000 131 /* AVD Toggle Enable during Burst Program */ 132 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 133 /* Address Data Multiplexing Shift */ 134 #define CSOR_NOR_ADM_MASK 0x0003E000 135 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 136 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 137 /* Type of the NOR device hooked */ 138 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 139 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 140 /* Time for Read Enable High to Output High Impedance */ 141 #define CSOR_NOR_TRHZ_MASK 0x0000001C 142 #define CSOR_NOR_TRHZ_SHIFT 2 143 #define CSOR_NOR_TRHZ_20 0x00000000 144 #define CSOR_NOR_TRHZ_40 0x00000004 145 #define CSOR_NOR_TRHZ_60 0x00000008 146 #define CSOR_NOR_TRHZ_80 0x0000000C 147 #define CSOR_NOR_TRHZ_100 0x00000010 148 /* Buffer control disable */ 149 #define CSOR_NOR_BCTLD 0x00000001 150 151 /* 152 * Chip Select Option Register - GPCM Mode 153 */ 154 /* GPCM Mode - Normal */ 155 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 156 /* GPCM Mode - GenericASIC */ 157 #define CSOR_GPCM_GPMODE_ASIC 0x80000000 158 /* Parity Mode odd/even */ 159 #define CSOR_GPCM_PARITY_EVEN 0x40000000 160 /* Parity Checking enable/disable */ 161 #define CSOR_GPCM_PAR_EN 0x20000000 162 /* GPCM Timeout Count */ 163 #define CSOR_GPCM_GPTO_MASK 0x0F000000 164 #define CSOR_GPCM_GPTO_SHIFT 24 165 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 166 /* GPCM External Access Termination mode for read access */ 167 #define CSOR_GPCM_RGETA_EXT 0x00080000 168 /* GPCM External Access Termination mode for write access */ 169 #define CSOR_GPCM_WGETA_EXT 0x00040000 170 /* Address Data Multiplexing Shift */ 171 #define CSOR_GPCM_ADM_MASK 0x0003E000 172 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 173 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 174 /* Generic ASIC Parity error indication delay */ 175 #define CSOR_GPCM_GAPERRD_MASK 0x00000180 176 #define CSOR_GPCM_GAPERRD_SHIFT 7 177 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 178 /* Time for Read Enable High to Output High Impedance */ 179 #define CSOR_GPCM_TRHZ_MASK 0x0000001C 180 #define CSOR_GPCM_TRHZ_20 0x00000000 181 #define CSOR_GPCM_TRHZ_40 0x00000004 182 #define CSOR_GPCM_TRHZ_60 0x00000008 183 #define CSOR_GPCM_TRHZ_80 0x0000000C 184 #define CSOR_GPCM_TRHZ_100 0x00000010 185 /* Buffer control disable */ 186 #define CSOR_GPCM_BCTLD 0x00000001 187 188 /* 189 * Flash Timing Registers (FTIM0 - FTIM2_CSn) 190 */ 191 /* 192 * FTIM0 - NAND Flash Mode 193 */ 194 #define FTIM0_NAND 0x7EFF3F3F 195 #define FTIM0_NAND_TCCST_SHIFT 25 196 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) 197 #define FTIM0_NAND_TWP_SHIFT 16 198 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) 199 #define FTIM0_NAND_TWCHT_SHIFT 8 200 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) 201 #define FTIM0_NAND_TWH_SHIFT 0 202 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) 203 /* 204 * FTIM1 - NAND Flash Mode 205 */ 206 #define FTIM1_NAND 0xFFFF3FFF 207 #define FTIM1_NAND_TADLE_SHIFT 24 208 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) 209 #define FTIM1_NAND_TWBE_SHIFT 16 210 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) 211 #define FTIM1_NAND_TRR_SHIFT 8 212 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) 213 #define FTIM1_NAND_TRP_SHIFT 0 214 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) 215 /* 216 * FTIM2 - NAND Flash Mode 217 */ 218 #define FTIM2_NAND 0x1FE1F8FF 219 #define FTIM2_NAND_TRAD_SHIFT 21 220 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) 221 #define FTIM2_NAND_TREH_SHIFT 11 222 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) 223 #define FTIM2_NAND_TWHRE_SHIFT 0 224 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) 225 /* 226 * FTIM3 - NAND Flash Mode 227 */ 228 #define FTIM3_NAND 0xFF000000 229 #define FTIM3_NAND_TWW_SHIFT 24 230 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) 231 232 /* 233 * FTIM0 - NOR Flash Mode 234 */ 235 #define FTIM0_NOR 0xF03F3F3F 236 #define FTIM0_NOR_TACSE_SHIFT 28 237 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) 238 #define FTIM0_NOR_TEADC_SHIFT 16 239 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) 240 #define FTIM0_NOR_TAVDS_SHIFT 8 241 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) 242 #define FTIM0_NOR_TEAHC_SHIFT 0 243 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) 244 /* 245 * FTIM1 - NOR Flash Mode 246 */ 247 #define FTIM1_NOR 0xFF003F3F 248 #define FTIM1_NOR_TACO_SHIFT 24 249 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) 250 #define FTIM1_NOR_TRAD_NOR_SHIFT 8 251 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) 252 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 253 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) 254 /* 255 * FTIM2 - NOR Flash Mode 256 */ 257 #define FTIM2_NOR 0x0F3CFCFF 258 #define FTIM2_NOR_TCS_SHIFT 24 259 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) 260 #define FTIM2_NOR_TCH_SHIFT 18 261 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) 262 #define FTIM2_NOR_TWPH_SHIFT 10 263 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) 264 #define FTIM2_NOR_TWP_SHIFT 0 265 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) 266 267 /* 268 * FTIM0 - Normal GPCM Mode 269 */ 270 #define FTIM0_GPCM 0xF03F3F3F 271 #define FTIM0_GPCM_TACSE_SHIFT 28 272 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) 273 #define FTIM0_GPCM_TEADC_SHIFT 16 274 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) 275 #define FTIM0_GPCM_TAVDS_SHIFT 8 276 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) 277 #define FTIM0_GPCM_TEAHC_SHIFT 0 278 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) 279 /* 280 * FTIM1 - Normal GPCM Mode 281 */ 282 #define FTIM1_GPCM 0xFF003F00 283 #define FTIM1_GPCM_TACO_SHIFT 24 284 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) 285 #define FTIM1_GPCM_TRAD_SHIFT 8 286 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) 287 /* 288 * FTIM2 - Normal GPCM Mode 289 */ 290 #define FTIM2_GPCM 0x0F3C00FF 291 #define FTIM2_GPCM_TCS_SHIFT 24 292 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) 293 #define FTIM2_GPCM_TCH_SHIFT 18 294 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) 295 #define FTIM2_GPCM_TWP_SHIFT 0 296 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) 297 298 /* 299 * Ready Busy Status Register (RB_STAT) 300 */ 301 /* CSn is READY */ 302 #define IFC_RB_STAT_READY_CS0 0x80000000 303 #define IFC_RB_STAT_READY_CS1 0x40000000 304 #define IFC_RB_STAT_READY_CS2 0x20000000 305 #define IFC_RB_STAT_READY_CS3 0x10000000 306 307 /* 308 * General Control Register (GCR) 309 */ 310 #define IFC_GCR_MASK 0x8000F800 311 /* reset all IFC hardware */ 312 #define IFC_GCR_SOFT_RST_ALL 0x80000000 313 /* Turnaroud Time of external buffer */ 314 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 315 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 316 317 /* 318 * Common Event and Error Status Register (CM_EVTER_STAT) 319 */ 320 /* Chip select error */ 321 #define IFC_CM_EVTER_STAT_CSER 0x80000000 322 323 /* 324 * Common Event and Error Enable Register (CM_EVTER_EN) 325 */ 326 /* Chip select error checking enable */ 327 #define IFC_CM_EVTER_EN_CSEREN 0x80000000 328 329 /* 330 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 331 */ 332 /* Chip select error interrupt enable */ 333 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 334 335 /* 336 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 337 */ 338 /* transaction type of error Read/Write */ 339 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 340 #define IFC_CM_ERATTR0_ERAID 0x0FF00000 341 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 342 343 /* 344 * Clock Control Register (CCR) 345 */ 346 #define IFC_CCR_MASK 0x0F0F8800 347 /* Clock division ratio */ 348 #define IFC_CCR_CLK_DIV_MASK 0x0F000000 349 #define IFC_CCR_CLK_DIV_SHIFT 24 350 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 351 /* IFC Clock Delay */ 352 #define IFC_CCR_CLK_DLY_MASK 0x000F0000 353 #define IFC_CCR_CLK_DLY_SHIFT 16 354 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 355 /* Invert IFC clock before sending out */ 356 #define IFC_CCR_INV_CLK_EN 0x00008000 357 /* Fedback IFC Clock */ 358 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 359 360 /* 361 * Clock Status Register (CSR) 362 */ 363 /* Clk is stable */ 364 #define IFC_CSR_CLK_STAT_STABLE 0x80000000 365 366 /* 367 * IFC_NAND Machine Specific Registers 368 */ 369 /* 370 * NAND Configuration Register (NCFGR) 371 */ 372 /* Auto Boot Mode */ 373 #define IFC_NAND_NCFGR_BOOT 0x80000000 374 /* SRAM INIT EN */ 375 #define IFC_NAND_SRAM_INIT_EN 0x20000000 376 /* Addressing Mode-ROW0+n/COL0 */ 377 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 378 /* Addressing Mode-ROW0+n/COL0+n */ 379 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 380 /* Number of loop iterations of FIR sequences for multi page operations */ 381 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 382 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 383 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 384 /* Number of wait cycles */ 385 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 386 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 387 388 /* 389 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 390 */ 391 /* General purpose FCM flash command bytes CMD0-CMD7 */ 392 #define IFC_NAND_FCR0_CMD0 0xFF000000 393 #define IFC_NAND_FCR0_CMD0_SHIFT 24 394 #define IFC_NAND_FCR0_CMD1 0x00FF0000 395 #define IFC_NAND_FCR0_CMD1_SHIFT 16 396 #define IFC_NAND_FCR0_CMD2 0x0000FF00 397 #define IFC_NAND_FCR0_CMD2_SHIFT 8 398 #define IFC_NAND_FCR0_CMD3 0x000000FF 399 #define IFC_NAND_FCR0_CMD3_SHIFT 0 400 #define IFC_NAND_FCR1_CMD4 0xFF000000 401 #define IFC_NAND_FCR1_CMD4_SHIFT 24 402 #define IFC_NAND_FCR1_CMD5 0x00FF0000 403 #define IFC_NAND_FCR1_CMD5_SHIFT 16 404 #define IFC_NAND_FCR1_CMD6 0x0000FF00 405 #define IFC_NAND_FCR1_CMD6_SHIFT 8 406 #define IFC_NAND_FCR1_CMD7 0x000000FF 407 #define IFC_NAND_FCR1_CMD7_SHIFT 0 408 409 /* 410 * Flash ROW and COL Address Register (ROWn, COLn) 411 */ 412 /* Main/spare region locator */ 413 #define IFC_NAND_COL_MS 0x80000000 414 /* Column Address */ 415 #define IFC_NAND_COL_CA_MASK 0x00000FFF 416 417 /* 418 * NAND Flash Byte Count Register (NAND_BC) 419 */ 420 /* Byte Count for read/Write */ 421 #define IFC_NAND_BC 0x000001FF 422 423 /* 424 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 425 */ 426 /* NAND Machine specific opcodes OP0-OP14*/ 427 #define IFC_NAND_FIR0_OP0 0xFC000000 428 #define IFC_NAND_FIR0_OP0_SHIFT 26 429 #define IFC_NAND_FIR0_OP1 0x03F00000 430 #define IFC_NAND_FIR0_OP1_SHIFT 20 431 #define IFC_NAND_FIR0_OP2 0x000FC000 432 #define IFC_NAND_FIR0_OP2_SHIFT 14 433 #define IFC_NAND_FIR0_OP3 0x00003F00 434 #define IFC_NAND_FIR0_OP3_SHIFT 8 435 #define IFC_NAND_FIR0_OP4 0x000000FC 436 #define IFC_NAND_FIR0_OP4_SHIFT 2 437 #define IFC_NAND_FIR1_OP5 0xFC000000 438 #define IFC_NAND_FIR1_OP5_SHIFT 26 439 #define IFC_NAND_FIR1_OP6 0x03F00000 440 #define IFC_NAND_FIR1_OP6_SHIFT 20 441 #define IFC_NAND_FIR1_OP7 0x000FC000 442 #define IFC_NAND_FIR1_OP7_SHIFT 14 443 #define IFC_NAND_FIR1_OP8 0x00003F00 444 #define IFC_NAND_FIR1_OP8_SHIFT 8 445 #define IFC_NAND_FIR1_OP9 0x000000FC 446 #define IFC_NAND_FIR1_OP9_SHIFT 2 447 #define IFC_NAND_FIR2_OP10 0xFC000000 448 #define IFC_NAND_FIR2_OP10_SHIFT 26 449 #define IFC_NAND_FIR2_OP11 0x03F00000 450 #define IFC_NAND_FIR2_OP11_SHIFT 20 451 #define IFC_NAND_FIR2_OP12 0x000FC000 452 #define IFC_NAND_FIR2_OP12_SHIFT 14 453 #define IFC_NAND_FIR2_OP13 0x00003F00 454 #define IFC_NAND_FIR2_OP13_SHIFT 8 455 #define IFC_NAND_FIR2_OP14 0x000000FC 456 #define IFC_NAND_FIR2_OP14_SHIFT 2 457 458 /* 459 * Instruction opcodes to be programmed 460 * in FIR registers- 6bits 461 */ 462 enum ifc_nand_fir_opcodes { 463 IFC_FIR_OP_NOP, 464 IFC_FIR_OP_CA0, 465 IFC_FIR_OP_CA1, 466 IFC_FIR_OP_CA2, 467 IFC_FIR_OP_CA3, 468 IFC_FIR_OP_RA0, 469 IFC_FIR_OP_RA1, 470 IFC_FIR_OP_RA2, 471 IFC_FIR_OP_RA3, 472 IFC_FIR_OP_CMD0, 473 IFC_FIR_OP_CMD1, 474 IFC_FIR_OP_CMD2, 475 IFC_FIR_OP_CMD3, 476 IFC_FIR_OP_CMD4, 477 IFC_FIR_OP_CMD5, 478 IFC_FIR_OP_CMD6, 479 IFC_FIR_OP_CMD7, 480 IFC_FIR_OP_CW0, 481 IFC_FIR_OP_CW1, 482 IFC_FIR_OP_CW2, 483 IFC_FIR_OP_CW3, 484 IFC_FIR_OP_CW4, 485 IFC_FIR_OP_CW5, 486 IFC_FIR_OP_CW6, 487 IFC_FIR_OP_CW7, 488 IFC_FIR_OP_WBCD, 489 IFC_FIR_OP_RBCD, 490 IFC_FIR_OP_BTRD, 491 IFC_FIR_OP_RDSTAT, 492 IFC_FIR_OP_NWAIT, 493 IFC_FIR_OP_WFR, 494 IFC_FIR_OP_SBRD, 495 IFC_FIR_OP_UA, 496 IFC_FIR_OP_RB, 497 }; 498 499 /* 500 * NAND Chip Select Register (NAND_CSEL) 501 */ 502 #define IFC_NAND_CSEL 0x0C000000 503 #define IFC_NAND_CSEL_SHIFT 26 504 #define IFC_NAND_CSEL_CS0 0x00000000 505 #define IFC_NAND_CSEL_CS1 0x04000000 506 #define IFC_NAND_CSEL_CS2 0x08000000 507 #define IFC_NAND_CSEL_CS3 0x0C000000 508 509 /* 510 * NAND Operation Sequence Start (NANDSEQ_STRT) 511 */ 512 /* NAND Flash Operation Start */ 513 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 514 /* Automatic Erase */ 515 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 516 /* Automatic Program */ 517 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 518 /* Automatic Copyback */ 519 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 520 /* Automatic Read Operation */ 521 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 522 /* Automatic Status Read */ 523 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 524 525 /* 526 * NAND Event and Error Status Register (NAND_EVTER_STAT) 527 */ 528 /* Operation Complete */ 529 #define IFC_NAND_EVTER_STAT_OPC 0x80000000 530 /* Flash Timeout Error */ 531 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 532 /* Write Protect Error */ 533 #define IFC_NAND_EVTER_STAT_WPER 0x04000000 534 /* ECC Error */ 535 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 536 /* RCW Load Done */ 537 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 538 /* Boot Loadr Done */ 539 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 540 /* Bad Block Indicator search select */ 541 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 542 543 /* 544 * NAND Flash Page Read Completion Event Status Register 545 * (PGRDCMPL_EVT_STAT) 546 */ 547 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 548 /* Small Page 0-15 Done */ 549 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 550 /* Large Page(2K) 0-3 Done */ 551 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 552 /* Large Page(4K) 0-1 Done */ 553 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 554 555 /* 556 * NAND Event and Error Enable Register (NAND_EVTER_EN) 557 */ 558 /* Operation complete event enable */ 559 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 560 /* Page read complete event enable */ 561 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 562 /* Flash Timeout error enable */ 563 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 564 /* Write Protect error enable */ 565 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 566 /* ECC error logging enable */ 567 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 568 569 /* 570 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 571 */ 572 /* Enable interrupt for operation complete */ 573 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 574 /* Enable interrupt for Page read complete */ 575 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 576 /* Enable interrupt for Flash timeout error */ 577 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 578 /* Enable interrupt for Write protect error */ 579 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 580 /* Enable interrupt for ECC error*/ 581 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 582 583 /* 584 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 585 */ 586 #define IFC_NAND_ERATTR0_MASK 0x0C080000 587 /* Error on CS0-3 for NAND */ 588 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 589 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 590 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 591 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 592 /* Transaction type of error Read/Write */ 593 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 594 595 /* 596 * NAND Flash Status Register (NAND_FSR) 597 */ 598 /* First byte of data read from read status op */ 599 #define IFC_NAND_NFSR_RS0 0xFF000000 600 /* Second byte of data read from read status op */ 601 #define IFC_NAND_NFSR_RS1 0x00FF0000 602 603 /* 604 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 605 */ 606 /* Number of ECC errors on sector n (n = 0-15) */ 607 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 608 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 609 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 610 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 611 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 612 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 613 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 614 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 615 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 616 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 617 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 618 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 619 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 620 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 621 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 622 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 623 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 624 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 625 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 626 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 627 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 628 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 629 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 630 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 631 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 632 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 633 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 634 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 635 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 636 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 637 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 638 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 639 640 /* 641 * NAND Control Register (NANDCR) 642 */ 643 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 644 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 645 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 646 647 /* 648 * NAND_AUTOBOOT_TRGR 649 */ 650 /* Trigger RCW load */ 651 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 652 /* Trigget Auto Boot */ 653 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 654 655 /* 656 * NAND_MDR 657 */ 658 /* 1st read data byte when opcode SBRD */ 659 #define IFC_NAND_MDR_RDATA0 0xFF000000 660 /* 2nd read data byte when opcode SBRD */ 661 #define IFC_NAND_MDR_RDATA1 0x00FF0000 662 663 /* 664 * NOR Machine Specific Registers 665 */ 666 /* 667 * NOR Event and Error Status Register (NOR_EVTER_STAT) 668 */ 669 /* NOR Command Sequence Operation Complete */ 670 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 671 /* Write Protect Error */ 672 #define IFC_NOR_EVTER_STAT_WPER 0x04000000 673 /* Command Sequence Timeout Error */ 674 #define IFC_NOR_EVTER_STAT_STOER 0x01000000 675 676 /* 677 * NOR Event and Error Enable Register (NOR_EVTER_EN) 678 */ 679 /* NOR Command Seq complete event enable */ 680 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 681 /* Write Protect Error Checking Enable */ 682 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 683 /* Timeout Error Enable */ 684 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 685 686 /* 687 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 688 */ 689 /* Enable interrupt for OPC complete */ 690 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 691 /* Enable interrupt for write protect error */ 692 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 693 /* Enable interrupt for timeout error */ 694 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 695 696 /* 697 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 698 */ 699 /* Source ID for error transaction */ 700 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 701 /* AXI ID for error transation */ 702 #define IFC_NOR_ERATTR0_ERAID 0x000FF000 703 /* Chip select corresponds to NOR error */ 704 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 705 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 706 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 707 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 708 /* Type of transaction read/write */ 709 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 710 711 /* 712 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 713 */ 714 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 715 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 716 717 /* 718 * NOR Control Register (NORCR) 719 */ 720 #define IFC_NORCR_MASK 0x0F0F0000 721 /* No. of Address/Data Phase */ 722 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 723 #define IFC_NORCR_NUM_PHASE_SHIFT 24 724 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 725 /* Sequence Timeout Count */ 726 #define IFC_NORCR_STOCNT_MASK 0x000F0000 727 #define IFC_NORCR_STOCNT_SHIFT 16 728 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 729 730 /* 731 * GPCM Machine specific registers 732 */ 733 /* 734 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 735 */ 736 /* Timeout error */ 737 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 738 /* Parity error */ 739 #define IFC_GPCM_EVTER_STAT_PER 0x01000000 740 741 /* 742 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 743 */ 744 /* Timeout error enable */ 745 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 746 /* Parity error enable */ 747 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 748 749 /* 750 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 751 */ 752 /* Enable Interrupt for timeout error */ 753 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 754 /* Enable Interrupt for Parity error */ 755 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 756 757 /* 758 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 759 */ 760 /* Source ID for error transaction */ 761 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 762 /* AXI ID for error transaction */ 763 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 764 /* Chip select corresponds to GPCM error */ 765 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 766 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 767 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 768 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 769 /* Type of transaction read/Write */ 770 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 771 772 /* 773 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 774 */ 775 /* On which beat of address/data parity error is observed */ 776 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 777 /* Parity Error on byte */ 778 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 779 /* Parity Error reported in addr or data phase */ 780 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 781 782 /* 783 * GPCM Status Register (GPCM_STAT) 784 */ 785 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 786 787 788 #ifndef __ASSEMBLY__ 789 #include <asm/io.h> 790 791 extern void print_ifc_regs(void); 792 extern void init_early_memctl_regs(void); 793 void init_final_memctl_regs(void); 794 795 #define IFC_RREGS_4KOFFSET (4*1024) 796 #define IFC_RREGS_64KOFFSET (64*1024) 797 798 #define IFC_FCM_BASE_ADDR \ 799 ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR) 800 801 #define get_ifc_cspr_ext(i) \ 802 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) 803 #define get_ifc_cspr(i) \ 804 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr)) 805 #define get_ifc_csor_ext(i) \ 806 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext)) 807 #define get_ifc_csor(i) \ 808 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor)) 809 #define get_ifc_amask(i) \ 810 (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask)) 811 #define get_ifc_ftim(i, j) \ 812 (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j])) 813 #define set_ifc_cspr_ext(i, v) \ 814 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) 815 #define set_ifc_cspr(i, v) \ 816 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v)) 817 #define set_ifc_csor_ext(i, v) \ 818 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v)) 819 #define set_ifc_csor(i, v) \ 820 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v)) 821 #define set_ifc_amask(i, v) \ 822 (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v)) 823 #define set_ifc_ftim(i, j, v) \ 824 (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v)) 825 826 enum ifc_chip_sel { 827 IFC_CS0, 828 IFC_CS1, 829 IFC_CS2, 830 IFC_CS3, 831 IFC_CS4, 832 IFC_CS5, 833 IFC_CS6, 834 IFC_CS7, 835 }; 836 837 enum ifc_ftims { 838 IFC_FTIM0, 839 IFC_FTIM1, 840 IFC_FTIM2, 841 IFC_FTIM3, 842 }; 843 844 /* 845 * IFC Controller NAND Machine registers 846 */ 847 struct fsl_ifc_nand { 848 u32 ncfgr; 849 u32 res1[0x4]; 850 u32 nand_fcr0; 851 u32 nand_fcr1; 852 u32 res2[0x8]; 853 u32 row0; 854 u32 res3; 855 u32 col0; 856 u32 res4; 857 u32 row1; 858 u32 res5; 859 u32 col1; 860 u32 res6; 861 u32 row2; 862 u32 res7; 863 u32 col2; 864 u32 res8; 865 u32 row3; 866 u32 res9; 867 u32 col3; 868 u32 res10[0x24]; 869 u32 nand_fbcr; 870 u32 res11; 871 u32 nand_fir0; 872 u32 nand_fir1; 873 u32 nand_fir2; 874 u32 res12[0x10]; 875 u32 nand_csel; 876 u32 res13; 877 u32 nandseq_strt; 878 u32 res14; 879 u32 nand_evter_stat; 880 u32 res15; 881 u32 pgrdcmpl_evt_stat; 882 u32 res16[0x2]; 883 u32 nand_evter_en; 884 u32 res17[0x2]; 885 u32 nand_evter_intr_en; 886 u32 nand_vol_addr_stat; 887 u32 res18; 888 u32 nand_erattr0; 889 u32 nand_erattr1; 890 u32 res19[0x10]; 891 u32 nand_fsr; 892 u32 res20[0x3]; 893 u32 nand_eccstat[6]; 894 u32 res21[0x1c]; 895 u32 nanndcr; 896 u32 res22[0x2]; 897 u32 nand_autoboot_trgr; 898 u32 res23; 899 u32 nand_mdr; 900 u32 res24[0x1c]; 901 u32 nand_dll_lowcfg0; 902 u32 nand_dll_lowcfg1; 903 u32 res25; 904 u32 nand_dll_lowstat; 905 u32 res26[0x3C]; 906 }; 907 908 /* 909 * IFC controller NOR Machine registers 910 */ 911 struct fsl_ifc_nor { 912 u32 nor_evter_stat; 913 u32 res1[0x2]; 914 u32 nor_evter_en; 915 u32 res2[0x2]; 916 u32 nor_evter_intr_en; 917 u32 res3[0x2]; 918 u32 nor_erattr0; 919 u32 nor_erattr1; 920 u32 nor_erattr2; 921 u32 res4[0x4]; 922 u32 norcr; 923 u32 res5[0xEF]; 924 }; 925 926 /* 927 * IFC controller GPCM Machine registers 928 */ 929 struct fsl_ifc_gpcm { 930 u32 gpcm_evter_stat; 931 u32 res1[0x2]; 932 u32 gpcm_evter_en; 933 u32 res2[0x2]; 934 u32 gpcm_evter_intr_en; 935 u32 res3[0x2]; 936 u32 gpcm_erattr0; 937 u32 gpcm_erattr1; 938 u32 gpcm_erattr2; 939 u32 gpcm_stat; 940 }; 941 942 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT 943 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) 944 #define IFC_CSPR_REG_LEN 148 945 #define IFC_AMASK_REG_LEN 144 946 #define IFC_CSOR_REG_LEN 144 947 #define IFC_FTIM_REG_LEN 576 948 949 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ 950 CONFIG_SYS_FSL_IFC_BANK_COUNT 951 #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ 952 CONFIG_SYS_FSL_IFC_BANK_COUNT 953 #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ 954 CONFIG_SYS_FSL_IFC_BANK_COUNT 955 #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ 956 CONFIG_SYS_FSL_IFC_BANK_COUNT 957 #else 958 #error IFC BANK count not vaild 959 #endif 960 #else 961 #error IFC BANK count not defined 962 #endif 963 964 struct fsl_ifc_cspr { 965 u32 cspr_ext; 966 u32 cspr; 967 u32 res; 968 }; 969 970 struct fsl_ifc_amask { 971 u32 amask; 972 u32 res[0x2]; 973 }; 974 975 struct fsl_ifc_csor { 976 u32 csor; 977 u32 csor_ext; 978 u32 res; 979 }; 980 981 struct fsl_ifc_ftim { 982 u32 ftim[4]; 983 u32 res[0x8]; 984 }; 985 986 /* 987 * IFC Controller Global Registers 988 * FCM - Flash control machine 989 */ 990 991 struct fsl_ifc_fcm { 992 u32 ifc_rev; 993 u32 res1[0x2]; 994 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 995 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; 996 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 997 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; 998 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 999 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; 1000 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 1001 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; 1002 u32 rb_stat; 1003 u32 rb_map; 1004 u32 wp_map; 1005 u32 ifc_gcr; 1006 u32 res7[0x2]; 1007 u32 cm_evter_stat; 1008 u32 res8[0x2]; 1009 u32 cm_evter_en; 1010 u32 res9[0x2]; 1011 u32 cm_evter_intr_en; 1012 u32 res10[0x2]; 1013 u32 cm_erattr0; 1014 u32 cm_erattr1; 1015 u32 res11[0x2]; 1016 u32 ifc_ccr; 1017 u32 ifc_csr; 1018 u32 ddr_ccr_low; 1019 }; 1020 1021 struct fsl_ifc_runtime { 1022 struct fsl_ifc_nand ifc_nand; 1023 struct fsl_ifc_nor ifc_nor; 1024 struct fsl_ifc_gpcm ifc_gpcm; 1025 }; 1026 1027 struct fsl_ifc { 1028 struct fsl_ifc_fcm *gregs; 1029 struct fsl_ifc_runtime *rregs; 1030 }; 1031 1032 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1033 #undef CSPR_MSEL_NOR 1034 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM 1035 #endif 1036 #endif /* CONFIG_FSL_IFC */ 1037 1038 #endif /* __ASSEMBLY__ */ 1039 #endif /* __FSL_IFC_H */ 1040