1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Author: Dipen Dudhat <dipen.dudhat@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __FSL_IFC_H 9 #define __FSL_IFC_H 10 11 #ifdef CONFIG_FSL_IFC 12 #include <config.h> 13 #include <common.h> 14 15 #define FSL_IFC_V1_1_0 0x01010000 16 #define FSL_IFC_V2_0_0 0x02000000 17 18 #ifdef CONFIG_SYS_FSL_IFC_LE 19 #define ifc_in32(a) in_le32(a) 20 #define ifc_out32(a, v) out_le32(a, v) 21 #define ifc_in16(a) in_le16(a) 22 #elif defined(CONFIG_SYS_FSL_IFC_BE) 23 #define ifc_in32(a) in_be32(a) 24 #define ifc_out32(a, v) out_be32(a, v) 25 #define ifc_in16(a) in_be16(a) 26 #else 27 #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined 28 #endif 29 30 31 /* 32 * CSPR - Chip Select Property Register 33 */ 34 #define CSPR_BA 0xFFFF0000 35 #define CSPR_BA_SHIFT 16 36 #define CSPR_PORT_SIZE 0x00000180 37 #define CSPR_PORT_SIZE_SHIFT 7 38 /* Port Size 8 bit */ 39 #define CSPR_PORT_SIZE_8 0x00000080 40 /* Port Size 16 bit */ 41 #define CSPR_PORT_SIZE_16 0x00000100 42 /* Port Size 32 bit */ 43 #define CSPR_PORT_SIZE_32 0x00000180 44 /* Write Protect */ 45 #define CSPR_WP 0x00000040 46 #define CSPR_WP_SHIFT 6 47 /* Machine Select */ 48 #define CSPR_MSEL 0x00000006 49 #define CSPR_MSEL_SHIFT 1 50 /* NOR */ 51 #define CSPR_MSEL_NOR 0x00000000 52 /* NAND */ 53 #define CSPR_MSEL_NAND 0x00000002 54 /* GPCM */ 55 #define CSPR_MSEL_GPCM 0x00000004 56 /* Bank Valid */ 57 #define CSPR_V 0x00000001 58 #define CSPR_V_SHIFT 0 59 60 /* Convert an address into the right format for the CSPR Registers */ 61 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) 62 63 /* 64 * Address Mask Register 65 */ 66 #define IFC_AMASK_MASK 0xFFFF0000 67 #define IFC_AMASK_SHIFT 16 68 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ 69 (__ilog2(n) - IFC_AMASK_SHIFT)) 70 71 /* 72 * Chip Select Option Register IFC_NAND Machine 73 */ 74 /* Enable ECC Encoder */ 75 #define CSOR_NAND_ECC_ENC_EN 0x80000000 76 #define CSOR_NAND_ECC_MODE_MASK 0x30000000 77 /* 4 bit correction per 520 Byte sector */ 78 #define CSOR_NAND_ECC_MODE_4 0x00000000 79 /* 8 bit correction per 528 Byte sector */ 80 #define CSOR_NAND_ECC_MODE_8 0x10000000 81 /* Enable ECC Decoder */ 82 #define CSOR_NAND_ECC_DEC_EN 0x04000000 83 /* Row Address Length */ 84 #define CSOR_NAND_RAL_MASK 0x01800000 85 #define CSOR_NAND_RAL_SHIFT 20 86 #define CSOR_NAND_RAL_1 0x00000000 87 #define CSOR_NAND_RAL_2 0x00800000 88 #define CSOR_NAND_RAL_3 0x01000000 89 #define CSOR_NAND_RAL_4 0x01800000 90 /* Page Size 512b, 2k, 4k */ 91 #define CSOR_NAND_PGS_MASK 0x00180000 92 #define CSOR_NAND_PGS_SHIFT 16 93 #define CSOR_NAND_PGS_512 0x00000000 94 #define CSOR_NAND_PGS_2K 0x00080000 95 #define CSOR_NAND_PGS_4K 0x00100000 96 #define CSOR_NAND_PGS_8K 0x00180000 97 /* Spare region Size */ 98 #define CSOR_NAND_SPRZ_MASK 0x0000E000 99 #define CSOR_NAND_SPRZ_SHIFT 13 100 #define CSOR_NAND_SPRZ_16 0x00000000 101 #define CSOR_NAND_SPRZ_64 0x00002000 102 #define CSOR_NAND_SPRZ_128 0x00004000 103 #define CSOR_NAND_SPRZ_210 0x00006000 104 #define CSOR_NAND_SPRZ_218 0x00008000 105 #define CSOR_NAND_SPRZ_224 0x0000A000 106 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 107 /* Pages Per Block */ 108 #define CSOR_NAND_PB_MASK 0x00000700 109 #define CSOR_NAND_PB_SHIFT 8 110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) 111 /* Time for Read Enable High to Output High Impedance */ 112 #define CSOR_NAND_TRHZ_MASK 0x0000001C 113 #define CSOR_NAND_TRHZ_SHIFT 2 114 #define CSOR_NAND_TRHZ_20 0x00000000 115 #define CSOR_NAND_TRHZ_40 0x00000004 116 #define CSOR_NAND_TRHZ_60 0x00000008 117 #define CSOR_NAND_TRHZ_80 0x0000000C 118 #define CSOR_NAND_TRHZ_100 0x00000010 119 /* Buffer control disable */ 120 #define CSOR_NAND_BCTLD 0x00000001 121 122 /* 123 * Chip Select Option Register - NOR Flash Mode 124 */ 125 /* Enable Address shift Mode */ 126 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 127 /* Page Read Enable from NOR device */ 128 #define CSOR_NOR_PGRD_EN 0x10000000 129 /* AVD Toggle Enable during Burst Program */ 130 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 131 /* Address Data Multiplexing Shift */ 132 #define CSOR_NOR_ADM_MASK 0x0003E000 133 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 134 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) 135 /* Type of the NOR device hooked */ 136 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 137 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 138 /* Time for Read Enable High to Output High Impedance */ 139 #define CSOR_NOR_TRHZ_MASK 0x0000001C 140 #define CSOR_NOR_TRHZ_SHIFT 2 141 #define CSOR_NOR_TRHZ_20 0x00000000 142 #define CSOR_NOR_TRHZ_40 0x00000004 143 #define CSOR_NOR_TRHZ_60 0x00000008 144 #define CSOR_NOR_TRHZ_80 0x0000000C 145 #define CSOR_NOR_TRHZ_100 0x00000010 146 /* Buffer control disable */ 147 #define CSOR_NOR_BCTLD 0x00000001 148 149 /* 150 * Chip Select Option Register - GPCM Mode 151 */ 152 /* GPCM Mode - Normal */ 153 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 154 /* GPCM Mode - GenericASIC */ 155 #define CSOR_GPCM_GPMODE_ASIC 0x80000000 156 /* Parity Mode odd/even */ 157 #define CSOR_GPCM_PARITY_EVEN 0x40000000 158 /* Parity Checking enable/disable */ 159 #define CSOR_GPCM_PAR_EN 0x20000000 160 /* GPCM Timeout Count */ 161 #define CSOR_GPCM_GPTO_MASK 0x0F000000 162 #define CSOR_GPCM_GPTO_SHIFT 24 163 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) 164 /* GPCM External Access Termination mode for read access */ 165 #define CSOR_GPCM_RGETA_EXT 0x00080000 166 /* GPCM External Access Termination mode for write access */ 167 #define CSOR_GPCM_WGETA_EXT 0x00040000 168 /* Address Data Multiplexing Shift */ 169 #define CSOR_GPCM_ADM_MASK 0x0003E000 170 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 171 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) 172 /* Generic ASIC Parity error indication delay */ 173 #define CSOR_GPCM_GAPERRD_MASK 0x00000180 174 #define CSOR_GPCM_GAPERRD_SHIFT 7 175 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) 176 /* Time for Read Enable High to Output High Impedance */ 177 #define CSOR_GPCM_TRHZ_MASK 0x0000001C 178 #define CSOR_GPCM_TRHZ_20 0x00000000 179 #define CSOR_GPCM_TRHZ_40 0x00000004 180 #define CSOR_GPCM_TRHZ_60 0x00000008 181 #define CSOR_GPCM_TRHZ_80 0x0000000C 182 #define CSOR_GPCM_TRHZ_100 0x00000010 183 /* Buffer control disable */ 184 #define CSOR_GPCM_BCTLD 0x00000001 185 186 /* 187 * Flash Timing Registers (FTIM0 - FTIM2_CSn) 188 */ 189 /* 190 * FTIM0 - NAND Flash Mode 191 */ 192 #define FTIM0_NAND 0x7EFF3F3F 193 #define FTIM0_NAND_TCCST_SHIFT 25 194 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) 195 #define FTIM0_NAND_TWP_SHIFT 16 196 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) 197 #define FTIM0_NAND_TWCHT_SHIFT 8 198 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) 199 #define FTIM0_NAND_TWH_SHIFT 0 200 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) 201 /* 202 * FTIM1 - NAND Flash Mode 203 */ 204 #define FTIM1_NAND 0xFFFF3FFF 205 #define FTIM1_NAND_TADLE_SHIFT 24 206 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) 207 #define FTIM1_NAND_TWBE_SHIFT 16 208 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) 209 #define FTIM1_NAND_TRR_SHIFT 8 210 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) 211 #define FTIM1_NAND_TRP_SHIFT 0 212 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) 213 /* 214 * FTIM2 - NAND Flash Mode 215 */ 216 #define FTIM2_NAND 0x1FE1F8FF 217 #define FTIM2_NAND_TRAD_SHIFT 21 218 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) 219 #define FTIM2_NAND_TREH_SHIFT 11 220 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) 221 #define FTIM2_NAND_TWHRE_SHIFT 0 222 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) 223 /* 224 * FTIM3 - NAND Flash Mode 225 */ 226 #define FTIM3_NAND 0xFF000000 227 #define FTIM3_NAND_TWW_SHIFT 24 228 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) 229 230 /* 231 * FTIM0 - NOR Flash Mode 232 */ 233 #define FTIM0_NOR 0xF03F3F3F 234 #define FTIM0_NOR_TACSE_SHIFT 28 235 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) 236 #define FTIM0_NOR_TEADC_SHIFT 16 237 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) 238 #define FTIM0_NOR_TAVDS_SHIFT 8 239 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) 240 #define FTIM0_NOR_TEAHC_SHIFT 0 241 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) 242 /* 243 * FTIM1 - NOR Flash Mode 244 */ 245 #define FTIM1_NOR 0xFF003F3F 246 #define FTIM1_NOR_TACO_SHIFT 24 247 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) 248 #define FTIM1_NOR_TRAD_NOR_SHIFT 8 249 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) 250 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 251 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) 252 /* 253 * FTIM2 - NOR Flash Mode 254 */ 255 #define FTIM2_NOR 0x0F3CFCFF 256 #define FTIM2_NOR_TCS_SHIFT 24 257 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) 258 #define FTIM2_NOR_TCH_SHIFT 18 259 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) 260 #define FTIM2_NOR_TWPH_SHIFT 10 261 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) 262 #define FTIM2_NOR_TWP_SHIFT 0 263 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) 264 265 /* 266 * FTIM0 - Normal GPCM Mode 267 */ 268 #define FTIM0_GPCM 0xF03F3F3F 269 #define FTIM0_GPCM_TACSE_SHIFT 28 270 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) 271 #define FTIM0_GPCM_TEADC_SHIFT 16 272 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) 273 #define FTIM0_GPCM_TAVDS_SHIFT 8 274 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) 275 #define FTIM0_GPCM_TEAHC_SHIFT 0 276 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) 277 /* 278 * FTIM1 - Normal GPCM Mode 279 */ 280 #define FTIM1_GPCM 0xFF003F00 281 #define FTIM1_GPCM_TACO_SHIFT 24 282 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) 283 #define FTIM1_GPCM_TRAD_SHIFT 8 284 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) 285 /* 286 * FTIM2 - Normal GPCM Mode 287 */ 288 #define FTIM2_GPCM 0x0F3C00FF 289 #define FTIM2_GPCM_TCS_SHIFT 24 290 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) 291 #define FTIM2_GPCM_TCH_SHIFT 18 292 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) 293 #define FTIM2_GPCM_TWP_SHIFT 0 294 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) 295 296 /* 297 * Ready Busy Status Register (RB_STAT) 298 */ 299 /* CSn is READY */ 300 #define IFC_RB_STAT_READY_CS0 0x80000000 301 #define IFC_RB_STAT_READY_CS1 0x40000000 302 #define IFC_RB_STAT_READY_CS2 0x20000000 303 #define IFC_RB_STAT_READY_CS3 0x10000000 304 305 /* 306 * General Control Register (GCR) 307 */ 308 #define IFC_GCR_MASK 0x8000F800 309 /* reset all IFC hardware */ 310 #define IFC_GCR_SOFT_RST_ALL 0x80000000 311 /* Turnaroud Time of external buffer */ 312 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 313 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 314 315 /* 316 * Common Event and Error Status Register (CM_EVTER_STAT) 317 */ 318 /* Chip select error */ 319 #define IFC_CM_EVTER_STAT_CSER 0x80000000 320 321 /* 322 * Common Event and Error Enable Register (CM_EVTER_EN) 323 */ 324 /* Chip select error checking enable */ 325 #define IFC_CM_EVTER_EN_CSEREN 0x80000000 326 327 /* 328 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) 329 */ 330 /* Chip select error interrupt enable */ 331 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 332 333 /* 334 * Common Transfer Error Attribute Register-0 (CM_ERATTR0) 335 */ 336 /* transaction type of error Read/Write */ 337 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 338 #define IFC_CM_ERATTR0_ERAID 0x0FF00000 339 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 340 341 /* 342 * Clock Control Register (CCR) 343 */ 344 #define IFC_CCR_MASK 0x0F0F8800 345 /* Clock division ratio */ 346 #define IFC_CCR_CLK_DIV_MASK 0x0F000000 347 #define IFC_CCR_CLK_DIV_SHIFT 24 348 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) 349 /* IFC Clock Delay */ 350 #define IFC_CCR_CLK_DLY_MASK 0x000F0000 351 #define IFC_CCR_CLK_DLY_SHIFT 16 352 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) 353 /* Invert IFC clock before sending out */ 354 #define IFC_CCR_INV_CLK_EN 0x00008000 355 /* Fedback IFC Clock */ 356 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 357 358 /* 359 * Clock Status Register (CSR) 360 */ 361 /* Clk is stable */ 362 #define IFC_CSR_CLK_STAT_STABLE 0x80000000 363 364 /* 365 * IFC_NAND Machine Specific Registers 366 */ 367 /* 368 * NAND Configuration Register (NCFGR) 369 */ 370 /* Auto Boot Mode */ 371 #define IFC_NAND_NCFGR_BOOT 0x80000000 372 /* SRAM INIT EN */ 373 #define IFC_NAND_SRAM_INIT_EN 0x20000000 374 /* Addressing Mode-ROW0+n/COL0 */ 375 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 376 /* Addressing Mode-ROW0+n/COL0+n */ 377 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 378 /* Number of loop iterations of FIR sequences for multi page operations */ 379 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 380 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 381 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) 382 /* Number of wait cycles */ 383 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF 384 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 385 386 /* 387 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) 388 */ 389 /* General purpose FCM flash command bytes CMD0-CMD7 */ 390 #define IFC_NAND_FCR0_CMD0 0xFF000000 391 #define IFC_NAND_FCR0_CMD0_SHIFT 24 392 #define IFC_NAND_FCR0_CMD1 0x00FF0000 393 #define IFC_NAND_FCR0_CMD1_SHIFT 16 394 #define IFC_NAND_FCR0_CMD2 0x0000FF00 395 #define IFC_NAND_FCR0_CMD2_SHIFT 8 396 #define IFC_NAND_FCR0_CMD3 0x000000FF 397 #define IFC_NAND_FCR0_CMD3_SHIFT 0 398 #define IFC_NAND_FCR1_CMD4 0xFF000000 399 #define IFC_NAND_FCR1_CMD4_SHIFT 24 400 #define IFC_NAND_FCR1_CMD5 0x00FF0000 401 #define IFC_NAND_FCR1_CMD5_SHIFT 16 402 #define IFC_NAND_FCR1_CMD6 0x0000FF00 403 #define IFC_NAND_FCR1_CMD6_SHIFT 8 404 #define IFC_NAND_FCR1_CMD7 0x000000FF 405 #define IFC_NAND_FCR1_CMD7_SHIFT 0 406 407 /* 408 * Flash ROW and COL Address Register (ROWn, COLn) 409 */ 410 /* Main/spare region locator */ 411 #define IFC_NAND_COL_MS 0x80000000 412 /* Column Address */ 413 #define IFC_NAND_COL_CA_MASK 0x00000FFF 414 415 /* 416 * NAND Flash Byte Count Register (NAND_BC) 417 */ 418 /* Byte Count for read/Write */ 419 #define IFC_NAND_BC 0x000001FF 420 421 /* 422 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) 423 */ 424 /* NAND Machine specific opcodes OP0-OP14*/ 425 #define IFC_NAND_FIR0_OP0 0xFC000000 426 #define IFC_NAND_FIR0_OP0_SHIFT 26 427 #define IFC_NAND_FIR0_OP1 0x03F00000 428 #define IFC_NAND_FIR0_OP1_SHIFT 20 429 #define IFC_NAND_FIR0_OP2 0x000FC000 430 #define IFC_NAND_FIR0_OP2_SHIFT 14 431 #define IFC_NAND_FIR0_OP3 0x00003F00 432 #define IFC_NAND_FIR0_OP3_SHIFT 8 433 #define IFC_NAND_FIR0_OP4 0x000000FC 434 #define IFC_NAND_FIR0_OP4_SHIFT 2 435 #define IFC_NAND_FIR1_OP5 0xFC000000 436 #define IFC_NAND_FIR1_OP5_SHIFT 26 437 #define IFC_NAND_FIR1_OP6 0x03F00000 438 #define IFC_NAND_FIR1_OP6_SHIFT 20 439 #define IFC_NAND_FIR1_OP7 0x000FC000 440 #define IFC_NAND_FIR1_OP7_SHIFT 14 441 #define IFC_NAND_FIR1_OP8 0x00003F00 442 #define IFC_NAND_FIR1_OP8_SHIFT 8 443 #define IFC_NAND_FIR1_OP9 0x000000FC 444 #define IFC_NAND_FIR1_OP9_SHIFT 2 445 #define IFC_NAND_FIR2_OP10 0xFC000000 446 #define IFC_NAND_FIR2_OP10_SHIFT 26 447 #define IFC_NAND_FIR2_OP11 0x03F00000 448 #define IFC_NAND_FIR2_OP11_SHIFT 20 449 #define IFC_NAND_FIR2_OP12 0x000FC000 450 #define IFC_NAND_FIR2_OP12_SHIFT 14 451 #define IFC_NAND_FIR2_OP13 0x00003F00 452 #define IFC_NAND_FIR2_OP13_SHIFT 8 453 #define IFC_NAND_FIR2_OP14 0x000000FC 454 #define IFC_NAND_FIR2_OP14_SHIFT 2 455 456 /* 457 * Instruction opcodes to be programmed 458 * in FIR registers- 6bits 459 */ 460 enum ifc_nand_fir_opcodes { 461 IFC_FIR_OP_NOP, 462 IFC_FIR_OP_CA0, 463 IFC_FIR_OP_CA1, 464 IFC_FIR_OP_CA2, 465 IFC_FIR_OP_CA3, 466 IFC_FIR_OP_RA0, 467 IFC_FIR_OP_RA1, 468 IFC_FIR_OP_RA2, 469 IFC_FIR_OP_RA3, 470 IFC_FIR_OP_CMD0, 471 IFC_FIR_OP_CMD1, 472 IFC_FIR_OP_CMD2, 473 IFC_FIR_OP_CMD3, 474 IFC_FIR_OP_CMD4, 475 IFC_FIR_OP_CMD5, 476 IFC_FIR_OP_CMD6, 477 IFC_FIR_OP_CMD7, 478 IFC_FIR_OP_CW0, 479 IFC_FIR_OP_CW1, 480 IFC_FIR_OP_CW2, 481 IFC_FIR_OP_CW3, 482 IFC_FIR_OP_CW4, 483 IFC_FIR_OP_CW5, 484 IFC_FIR_OP_CW6, 485 IFC_FIR_OP_CW7, 486 IFC_FIR_OP_WBCD, 487 IFC_FIR_OP_RBCD, 488 IFC_FIR_OP_BTRD, 489 IFC_FIR_OP_RDSTAT, 490 IFC_FIR_OP_NWAIT, 491 IFC_FIR_OP_WFR, 492 IFC_FIR_OP_SBRD, 493 IFC_FIR_OP_UA, 494 IFC_FIR_OP_RB, 495 }; 496 497 /* 498 * NAND Chip Select Register (NAND_CSEL) 499 */ 500 #define IFC_NAND_CSEL 0x0C000000 501 #define IFC_NAND_CSEL_SHIFT 26 502 #define IFC_NAND_CSEL_CS0 0x00000000 503 #define IFC_NAND_CSEL_CS1 0x04000000 504 #define IFC_NAND_CSEL_CS2 0x08000000 505 #define IFC_NAND_CSEL_CS3 0x0C000000 506 507 /* 508 * NAND Operation Sequence Start (NANDSEQ_STRT) 509 */ 510 /* NAND Flash Operation Start */ 511 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 512 /* Automatic Erase */ 513 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 514 /* Automatic Program */ 515 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 516 /* Automatic Copyback */ 517 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 518 /* Automatic Read Operation */ 519 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 520 /* Automatic Status Read */ 521 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 522 523 /* 524 * NAND Event and Error Status Register (NAND_EVTER_STAT) 525 */ 526 /* Operation Complete */ 527 #define IFC_NAND_EVTER_STAT_OPC 0x80000000 528 /* Flash Timeout Error */ 529 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 530 /* Write Protect Error */ 531 #define IFC_NAND_EVTER_STAT_WPER 0x04000000 532 /* ECC Error */ 533 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 534 /* RCW Load Done */ 535 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 536 /* Boot Loadr Done */ 537 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 538 /* Bad Block Indicator search select */ 539 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 540 541 /* 542 * NAND Flash Page Read Completion Event Status Register 543 * (PGRDCMPL_EVT_STAT) 544 */ 545 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 546 /* Small Page 0-15 Done */ 547 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) 548 /* Large Page(2K) 0-3 Done */ 549 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) 550 /* Large Page(4K) 0-1 Done */ 551 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) 552 553 /* 554 * NAND Event and Error Enable Register (NAND_EVTER_EN) 555 */ 556 /* Operation complete event enable */ 557 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 558 /* Page read complete event enable */ 559 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 560 /* Flash Timeout error enable */ 561 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 562 /* Write Protect error enable */ 563 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 564 /* ECC error logging enable */ 565 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 566 567 /* 568 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) 569 */ 570 /* Enable interrupt for operation complete */ 571 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 572 /* Enable interrupt for Page read complete */ 573 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 574 /* Enable interrupt for Flash timeout error */ 575 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 576 /* Enable interrupt for Write protect error */ 577 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 578 /* Enable interrupt for ECC error*/ 579 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 580 581 /* 582 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) 583 */ 584 #define IFC_NAND_ERATTR0_MASK 0x0C080000 585 /* Error on CS0-3 for NAND */ 586 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 587 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 588 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 589 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 590 /* Transaction type of error Read/Write */ 591 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 592 593 /* 594 * NAND Flash Status Register (NAND_FSR) 595 */ 596 /* First byte of data read from read status op */ 597 #define IFC_NAND_NFSR_RS0 0xFF000000 598 /* Second byte of data read from read status op */ 599 #define IFC_NAND_NFSR_RS1 0x00FF0000 600 601 /* 602 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) 603 */ 604 /* Number of ECC errors on sector n (n = 0-15) */ 605 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 606 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 607 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 608 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 609 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 610 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 611 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F 612 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 613 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 614 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 615 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 616 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 617 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 618 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 619 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F 620 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 621 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 622 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 623 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 624 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 625 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 626 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 627 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F 628 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 629 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 630 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 631 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 632 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 633 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 634 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 635 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F 636 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 637 638 /* 639 * NAND Control Register (NANDCR) 640 */ 641 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 642 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 643 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) 644 645 /* 646 * NAND_AUTOBOOT_TRGR 647 */ 648 /* Trigger RCW load */ 649 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 650 /* Trigget Auto Boot */ 651 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 652 653 /* 654 * NAND_MDR 655 */ 656 /* 1st read data byte when opcode SBRD */ 657 #define IFC_NAND_MDR_RDATA0 0xFF000000 658 /* 2nd read data byte when opcode SBRD */ 659 #define IFC_NAND_MDR_RDATA1 0x00FF0000 660 661 /* 662 * NOR Machine Specific Registers 663 */ 664 /* 665 * NOR Event and Error Status Register (NOR_EVTER_STAT) 666 */ 667 /* NOR Command Sequence Operation Complete */ 668 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 669 /* Write Protect Error */ 670 #define IFC_NOR_EVTER_STAT_WPER 0x04000000 671 /* Command Sequence Timeout Error */ 672 #define IFC_NOR_EVTER_STAT_STOER 0x01000000 673 674 /* 675 * NOR Event and Error Enable Register (NOR_EVTER_EN) 676 */ 677 /* NOR Command Seq complete event enable */ 678 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 679 /* Write Protect Error Checking Enable */ 680 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 681 /* Timeout Error Enable */ 682 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 683 684 /* 685 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) 686 */ 687 /* Enable interrupt for OPC complete */ 688 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 689 /* Enable interrupt for write protect error */ 690 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 691 /* Enable interrupt for timeout error */ 692 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 693 694 /* 695 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) 696 */ 697 /* Source ID for error transaction */ 698 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 699 /* AXI ID for error transation */ 700 #define IFC_NOR_ERATTR0_ERAID 0x000FF000 701 /* Chip select corresponds to NOR error */ 702 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 703 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 704 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 705 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 706 /* Type of transaction read/write */ 707 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 708 709 /* 710 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) 711 */ 712 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 713 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 714 715 /* 716 * NOR Control Register (NORCR) 717 */ 718 #define IFC_NORCR_MASK 0x0F0F0000 719 /* No. of Address/Data Phase */ 720 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 721 #define IFC_NORCR_NUM_PHASE_SHIFT 24 722 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) 723 /* Sequence Timeout Count */ 724 #define IFC_NORCR_STOCNT_MASK 0x000F0000 725 #define IFC_NORCR_STOCNT_SHIFT 16 726 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) 727 728 /* 729 * GPCM Machine specific registers 730 */ 731 /* 732 * GPCM Event and Error Status Register (GPCM_EVTER_STAT) 733 */ 734 /* Timeout error */ 735 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 736 /* Parity error */ 737 #define IFC_GPCM_EVTER_STAT_PER 0x01000000 738 739 /* 740 * GPCM Event and Error Enable Register (GPCM_EVTER_EN) 741 */ 742 /* Timeout error enable */ 743 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 744 /* Parity error enable */ 745 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 746 747 /* 748 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) 749 */ 750 /* Enable Interrupt for timeout error */ 751 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 752 /* Enable Interrupt for Parity error */ 753 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 754 755 /* 756 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) 757 */ 758 /* Source ID for error transaction */ 759 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 760 /* AXI ID for error transaction */ 761 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 762 /* Chip select corresponds to GPCM error */ 763 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 764 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 765 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 766 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 767 /* Type of transaction read/Write */ 768 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 769 770 /* 771 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) 772 */ 773 /* On which beat of address/data parity error is observed */ 774 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 775 /* Parity Error on byte */ 776 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 777 /* Parity Error reported in addr or data phase */ 778 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 779 780 /* 781 * GPCM Status Register (GPCM_STAT) 782 */ 783 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ 784 785 786 #ifndef __ASSEMBLY__ 787 #include <asm/io.h> 788 789 extern void print_ifc_regs(void); 790 extern void init_early_memctl_regs(void); 791 void init_final_memctl_regs(void); 792 793 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) 794 795 #define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) 796 #define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) 797 #define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) 798 #define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) 799 #define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) 800 #define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) 801 802 #define set_ifc_cspr_ext(i, v) \ 803 (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) 804 #define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) 805 #define set_ifc_csor_ext(i, v) \ 806 (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) 807 #define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) 808 #define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) 809 #define set_ifc_ftim(i, j, v) \ 810 (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) 811 812 enum ifc_chip_sel { 813 IFC_CS0, 814 IFC_CS1, 815 IFC_CS2, 816 IFC_CS3, 817 IFC_CS4, 818 IFC_CS5, 819 IFC_CS6, 820 IFC_CS7, 821 }; 822 823 enum ifc_ftims { 824 IFC_FTIM0, 825 IFC_FTIM1, 826 IFC_FTIM2, 827 IFC_FTIM3, 828 }; 829 830 /* 831 * IFC Controller NAND Machine registers 832 */ 833 struct fsl_ifc_nand { 834 u32 ncfgr; 835 u32 res1[0x4]; 836 u32 nand_fcr0; 837 u32 nand_fcr1; 838 u32 res2[0x8]; 839 u32 row0; 840 u32 res3; 841 u32 col0; 842 u32 res4; 843 u32 row1; 844 u32 res5; 845 u32 col1; 846 u32 res6; 847 u32 row2; 848 u32 res7; 849 u32 col2; 850 u32 res8; 851 u32 row3; 852 u32 res9; 853 u32 col3; 854 u32 res10[0x24]; 855 u32 nand_fbcr; 856 u32 res11; 857 u32 nand_fir0; 858 u32 nand_fir1; 859 u32 nand_fir2; 860 u32 res12[0x10]; 861 u32 nand_csel; 862 u32 res13; 863 u32 nandseq_strt; 864 u32 res14; 865 u32 nand_evter_stat; 866 u32 res15; 867 u32 pgrdcmpl_evt_stat; 868 u32 res16[0x2]; 869 u32 nand_evter_en; 870 u32 res17[0x2]; 871 u32 nand_evter_intr_en; 872 u32 res18[0x2]; 873 u32 nand_erattr0; 874 u32 nand_erattr1; 875 u32 res19[0x10]; 876 u32 nand_fsr; 877 u32 res20; 878 u32 nand_eccstat[4]; 879 u32 res21[0x20]; 880 u32 nanndcr; 881 u32 res22[0x2]; 882 u32 nand_autoboot_trgr; 883 u32 res23; 884 u32 nand_mdr; 885 u32 res24[0x5C]; 886 }; 887 888 /* 889 * IFC controller NOR Machine registers 890 */ 891 struct fsl_ifc_nor { 892 u32 nor_evter_stat; 893 u32 res1[0x2]; 894 u32 nor_evter_en; 895 u32 res2[0x2]; 896 u32 nor_evter_intr_en; 897 u32 res3[0x2]; 898 u32 nor_erattr0; 899 u32 nor_erattr1; 900 u32 nor_erattr2; 901 u32 res4[0x4]; 902 u32 norcr; 903 u32 res5[0xEF]; 904 }; 905 906 /* 907 * IFC controller GPCM Machine registers 908 */ 909 struct fsl_ifc_gpcm { 910 u32 gpcm_evter_stat; 911 u32 res1[0x2]; 912 u32 gpcm_evter_en; 913 u32 res2[0x2]; 914 u32 gpcm_evter_intr_en; 915 u32 res3[0x2]; 916 u32 gpcm_erattr0; 917 u32 gpcm_erattr1; 918 u32 gpcm_erattr2; 919 u32 gpcm_stat; 920 u32 res4[0x1F3]; 921 }; 922 923 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT 924 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) 925 #define IFC_CSPR_REG_LEN 148 926 #define IFC_AMASK_REG_LEN 144 927 #define IFC_CSOR_REG_LEN 144 928 #define IFC_FTIM_REG_LEN 576 929 930 #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ 931 CONFIG_SYS_FSL_IFC_BANK_COUNT 932 #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ 933 CONFIG_SYS_FSL_IFC_BANK_COUNT 934 #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ 935 CONFIG_SYS_FSL_IFC_BANK_COUNT 936 #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ 937 CONFIG_SYS_FSL_IFC_BANK_COUNT 938 #else 939 #error IFC BANK count not vaild 940 #endif 941 #else 942 #error IFC BANK count not defined 943 #endif 944 945 struct fsl_ifc_cspr { 946 u32 cspr_ext; 947 u32 cspr; 948 u32 res; 949 }; 950 951 struct fsl_ifc_amask { 952 u32 amask; 953 u32 res[0x2]; 954 }; 955 956 struct fsl_ifc_csor { 957 u32 csor; 958 u32 csor_ext; 959 u32 res; 960 }; 961 962 struct fsl_ifc_ftim { 963 u32 ftim[4]; 964 u32 res[0x8]; 965 }; 966 967 /* 968 * IFC Controller Registers 969 */ 970 struct fsl_ifc { 971 u32 ifc_rev; 972 u32 res1[0x2]; 973 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 974 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; 975 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 976 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; 977 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 978 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; 979 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; 980 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; 981 u32 rb_stat; 982 u32 res6[0x2]; 983 u32 ifc_gcr; 984 u32 res7[0x2]; 985 u32 cm_evter_stat; 986 u32 res8[0x2]; 987 u32 cm_evter_en; 988 u32 res9[0x2]; 989 u32 cm_evter_intr_en; 990 u32 res10[0x2]; 991 u32 cm_erattr0; 992 u32 cm_erattr1; 993 u32 res11[0x2]; 994 u32 ifc_ccr; 995 u32 ifc_csr; 996 u32 res12[0x2EB]; 997 struct fsl_ifc_nand ifc_nand; 998 struct fsl_ifc_nor ifc_nor; 999 struct fsl_ifc_gpcm ifc_gpcm; 1000 }; 1001 1002 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1003 #undef CSPR_MSEL_NOR 1004 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM 1005 #endif 1006 #endif /* CONFIG_FSL_IFC */ 1007 1008 #endif /* __ASSEMBLY__ */ 1009 #endif /* __FSL_IFC_H */ 1010