xref: /openbmc/u-boot/include/fsl_esdhc.h (revision 657fd2d0)
1 /*
2  * FSL SD/MMC Defines
3  *-------------------------------------------------------------------
4  *
5  * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef  __FSL_ESDHC_H__
11 #define	__FSL_ESDHC_H__
12 
13 #include <asm/errno.h>
14 #include <asm/byteorder.h>
15 
16 /* needed for the mmc_cfg definition */
17 #include <mmc.h>
18 
19 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
20 #include "../board/freescale/common/qixis.h"
21 #endif
22 
23 /* FSL eSDHC-specific constants */
24 #define SYSCTL			0x0002e02c
25 #define SYSCTL_INITA		0x08000000
26 #define SYSCTL_TIMEOUT_MASK	0x000f0000
27 #define SYSCTL_CLOCK_MASK	0x0000fff0
28 #define SYSCTL_CKEN		0x00000008
29 #define SYSCTL_PEREN		0x00000004
30 #define SYSCTL_HCKEN		0x00000002
31 #define SYSCTL_IPGEN		0x00000001
32 #define SYSCTL_RSTA		0x01000000
33 #define SYSCTL_RSTC		0x02000000
34 #define SYSCTL_RSTD		0x04000000
35 
36 #define IRQSTAT			0x0002e030
37 #define IRQSTAT_DMAE		(0x10000000)
38 #define IRQSTAT_AC12E		(0x01000000)
39 #define IRQSTAT_DEBE		(0x00400000)
40 #define IRQSTAT_DCE		(0x00200000)
41 #define IRQSTAT_DTOE		(0x00100000)
42 #define IRQSTAT_CIE		(0x00080000)
43 #define IRQSTAT_CEBE		(0x00040000)
44 #define IRQSTAT_CCE		(0x00020000)
45 #define IRQSTAT_CTOE		(0x00010000)
46 #define IRQSTAT_CINT		(0x00000100)
47 #define IRQSTAT_CRM		(0x00000080)
48 #define IRQSTAT_CINS		(0x00000040)
49 #define IRQSTAT_BRR		(0x00000020)
50 #define IRQSTAT_BWR		(0x00000010)
51 #define IRQSTAT_DINT		(0x00000008)
52 #define IRQSTAT_BGE		(0x00000004)
53 #define IRQSTAT_TC		(0x00000002)
54 #define IRQSTAT_CC		(0x00000001)
55 
56 #define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
57 #define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
58 				IRQSTAT_DMAE)
59 #define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
60 
61 #define IRQSTATEN		0x0002e034
62 #define IRQSTATEN_DMAE		(0x10000000)
63 #define IRQSTATEN_AC12E		(0x01000000)
64 #define IRQSTATEN_DEBE		(0x00400000)
65 #define IRQSTATEN_DCE		(0x00200000)
66 #define IRQSTATEN_DTOE		(0x00100000)
67 #define IRQSTATEN_CIE		(0x00080000)
68 #define IRQSTATEN_CEBE		(0x00040000)
69 #define IRQSTATEN_CCE		(0x00020000)
70 #define IRQSTATEN_CTOE		(0x00010000)
71 #define IRQSTATEN_CINT		(0x00000100)
72 #define IRQSTATEN_CRM		(0x00000080)
73 #define IRQSTATEN_CINS		(0x00000040)
74 #define IRQSTATEN_BRR		(0x00000020)
75 #define IRQSTATEN_BWR		(0x00000010)
76 #define IRQSTATEN_DINT		(0x00000008)
77 #define IRQSTATEN_BGE		(0x00000004)
78 #define IRQSTATEN_TC		(0x00000002)
79 #define IRQSTATEN_CC		(0x00000001)
80 
81 #define ESDHCCTL		0x0002e40c
82 #define ESDHCCTL_PCS		(0x00080000)
83 
84 #define PRSSTAT			0x0002e024
85 #define PRSSTAT_DAT0		(0x01000000)
86 #define PRSSTAT_CLSL		(0x00800000)
87 #define PRSSTAT_WPSPL		(0x00080000)
88 #define PRSSTAT_CDPL		(0x00040000)
89 #define PRSSTAT_CINS		(0x00010000)
90 #define PRSSTAT_BREN		(0x00000800)
91 #define PRSSTAT_BWEN		(0x00000400)
92 #define PRSSTAT_SDSTB		(0X00000008)
93 #define PRSSTAT_DLA		(0x00000004)
94 #define PRSSTAT_CICHB		(0x00000002)
95 #define PRSSTAT_CIDHB		(0x00000001)
96 
97 #define PROCTL			0x0002e028
98 #define PROCTL_INIT		0x00000020
99 #define PROCTL_DTW_4		0x00000002
100 #define PROCTL_DTW_8		0x00000004
101 
102 #define CMDARG			0x0002e008
103 
104 #define XFERTYP			0x0002e00c
105 #define XFERTYP_CMD(x)		((x & 0x3f) << 24)
106 #define XFERTYP_CMDTYP_NORMAL	0x0
107 #define XFERTYP_CMDTYP_SUSPEND	0x00400000
108 #define XFERTYP_CMDTYP_RESUME	0x00800000
109 #define XFERTYP_CMDTYP_ABORT	0x00c00000
110 #define XFERTYP_DPSEL		0x00200000
111 #define XFERTYP_CICEN		0x00100000
112 #define XFERTYP_CCCEN		0x00080000
113 #define XFERTYP_RSPTYP_NONE	0
114 #define XFERTYP_RSPTYP_136	0x00010000
115 #define XFERTYP_RSPTYP_48	0x00020000
116 #define XFERTYP_RSPTYP_48_BUSY	0x00030000
117 #define XFERTYP_MSBSEL		0x00000020
118 #define XFERTYP_DTDSEL		0x00000010
119 #define XFERTYP_DDREN		0x00000008
120 #define XFERTYP_AC12EN		0x00000004
121 #define XFERTYP_BCEN		0x00000002
122 #define XFERTYP_DMAEN		0x00000001
123 
124 #define CINS_TIMEOUT		1000
125 #define PIO_TIMEOUT		100000
126 
127 #define DSADDR		0x2e004
128 
129 #define CMDRSP0		0x2e010
130 #define CMDRSP1		0x2e014
131 #define CMDRSP2		0x2e018
132 #define CMDRSP3		0x2e01c
133 
134 #define DATPORT		0x2e020
135 
136 #define WML		0x2e044
137 #define WML_WRITE	0x00010000
138 #ifdef CONFIG_FSL_SDHC_V2_3
139 #define WML_RD_WML_MAX		0x80
140 #define WML_WR_WML_MAX		0x80
141 #define WML_RD_WML_MAX_VAL	0x0
142 #define WML_WR_WML_MAX_VAL	0x0
143 #define WML_RD_WML_MASK		0x7f
144 #define WML_WR_WML_MASK		0x7f0000
145 #else
146 #define WML_RD_WML_MAX		0x10
147 #define WML_WR_WML_MAX		0x80
148 #define WML_RD_WML_MAX_VAL	0x10
149 #define WML_WR_WML_MAX_VAL	0x80
150 #define WML_RD_WML_MASK	0xff
151 #define WML_WR_WML_MASK	0xff0000
152 #endif
153 
154 #define BLKATTR		0x2e004
155 #define BLKATTR_CNT(x)	((x & 0xffff) << 16)
156 #define BLKATTR_SIZE(x)	(x & 0x1fff)
157 #define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
158 
159 #define ESDHC_HOSTCAPBLT_VS18	0x04000000
160 #define ESDHC_HOSTCAPBLT_VS30	0x02000000
161 #define ESDHC_HOSTCAPBLT_VS33	0x01000000
162 #define ESDHC_HOSTCAPBLT_SRS	0x00800000
163 #define ESDHC_HOSTCAPBLT_DMAS	0x00400000
164 #define ESDHC_HOSTCAPBLT_HSS	0x00200000
165 
166 #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
167 
168 struct fsl_esdhc_cfg {
169 #ifdef CONFIG_LS2085A
170 	u64	esdhc_base;
171 #else
172 	u32	esdhc_base;
173 #endif
174 	u32	sdhc_clk;
175 	u8	max_bus_width;
176 	struct mmc_config cfg;
177 };
178 
179 /* Select the correct accessors depending on endianess */
180 #if defined CONFIG_SYS_FSL_ESDHC_LE
181 #define esdhc_read32		in_le32
182 #define esdhc_write32		out_le32
183 #define esdhc_clrsetbits32	clrsetbits_le32
184 #define esdhc_clrbits32		clrbits_le32
185 #define esdhc_setbits32		setbits_le32
186 #elif defined(CONFIG_SYS_FSL_ESDHC_BE)
187 #define esdhc_read32            in_be32
188 #define esdhc_write32           out_be32
189 #define esdhc_clrsetbits32      clrsetbits_be32
190 #define esdhc_clrbits32         clrbits_be32
191 #define esdhc_setbits32         setbits_be32
192 #elif __BYTE_ORDER == __LITTLE_ENDIAN
193 #define esdhc_read32		in_le32
194 #define esdhc_write32		out_le32
195 #define esdhc_clrsetbits32	clrsetbits_le32
196 #define esdhc_clrbits32		clrbits_le32
197 #define esdhc_setbits32		setbits_le32
198 #elif __BYTE_ORDER == __BIG_ENDIAN
199 #define esdhc_read32		in_be32
200 #define esdhc_write32		out_be32
201 #define esdhc_clrsetbits32	clrsetbits_be32
202 #define esdhc_clrbits32		clrbits_be32
203 #define esdhc_setbits32		setbits_be32
204 #else
205 #error "Endianess is not defined: please fix to continue"
206 #endif
207 
208 #ifdef CONFIG_FSL_ESDHC
209 int fsl_esdhc_mmc_init(bd_t *bis);
210 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
211 void fdt_fixup_esdhc(void *blob, bd_t *bd);
212 #else
213 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
214 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
215 #endif /* CONFIG_FSL_ESDHC */
216 void __noreturn mmc_boot(void);
217 void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
218 
219 #endif  /* __FSL_ESDHC_H__ */
220