1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef FSL_DDR_MEMCTL_H 10 #define FSL_DDR_MEMCTL_H 11 12 /* 13 * Pick a basic DDR Technology. 14 */ 15 #include <ddr_spd.h> 16 #include <fsl_ddrc_version.h> 17 18 #define SDRAM_TYPE_DDR1 2 19 #define SDRAM_TYPE_DDR2 3 20 #define SDRAM_TYPE_LPDDR1 6 21 #define SDRAM_TYPE_DDR3 7 22 #define SDRAM_TYPE_DDR4 5 23 24 #define DDR_BL4 4 /* burst length 4 */ 25 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ 26 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 27 #define DDR_BL8 8 /* burst length 8 */ 28 29 #define DDR3_RTT_OFF 0 30 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ 31 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ 32 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ 33 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ 34 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ 35 36 #define DDR2_RTT_OFF 0 37 #define DDR2_RTT_75_OHM 1 38 #define DDR2_RTT_150_OHM 2 39 #define DDR2_RTT_50_OHM 3 40 41 #if defined(CONFIG_SYS_FSL_DDR1) 42 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) 43 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; 44 #ifndef CONFIG_FSL_SDRAM_TYPE 45 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 46 #endif 47 #elif defined(CONFIG_SYS_FSL_DDR2) 48 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) 49 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; 50 #ifndef CONFIG_FSL_SDRAM_TYPE 51 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 52 #endif 53 #elif defined(CONFIG_SYS_FSL_DDR3) 54 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ 55 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; 56 #ifndef CONFIG_FSL_SDRAM_TYPE 57 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 58 #endif 59 #elif defined(CONFIG_SYS_FSL_DDR4) 60 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ 61 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; 62 #ifndef CONFIG_FSL_SDRAM_TYPE 63 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 64 #endif 65 #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ 66 67 #define FSL_DDR_ODT_NEVER 0x0 68 #define FSL_DDR_ODT_CS 0x1 69 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2 70 #define FSL_DDR_ODT_OTHER_DIMM 0x3 71 #define FSL_DDR_ODT_ALL 0x4 72 #define FSL_DDR_ODT_SAME_DIMM 0x5 73 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 74 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 75 76 /* define bank(chip select) interleaving mode */ 77 #define FSL_DDR_CS0_CS1 0x40 78 #define FSL_DDR_CS2_CS3 0x20 79 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) 80 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) 81 82 /* define memory controller interleaving mode */ 83 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 84 #define FSL_DDR_PAGE_INTERLEAVING 0x1 85 #define FSL_DDR_BANK_INTERLEAVING 0x2 86 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 87 #define FSL_DDR_256B_INTERLEAVING 0x8 88 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA 89 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC 90 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD 91 /* placeholder for 4-way interleaving */ 92 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A 93 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C 94 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D 95 96 #define SDRAM_CS_CONFIG_EN 0x80000000 97 98 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 99 */ 100 #define SDRAM_CFG_MEM_EN 0x80000000 101 #define SDRAM_CFG_SREN 0x40000000 102 #define SDRAM_CFG_ECC_EN 0x20000000 103 #define SDRAM_CFG_RD_EN 0x10000000 104 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 105 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 106 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 107 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 108 #define SDRAM_CFG_DYN_PWR 0x00200000 109 #define SDRAM_CFG_DBW_MASK 0x00180000 110 #define SDRAM_CFG_DBW_SHIFT 19 111 #define SDRAM_CFG_32_BE 0x00080000 112 #define SDRAM_CFG_16_BE 0x00100000 113 #define SDRAM_CFG_8_BE 0x00040000 114 #define SDRAM_CFG_NCAP 0x00020000 115 #define SDRAM_CFG_2T_EN 0x00008000 116 #define SDRAM_CFG_BI 0x00000001 117 118 #define SDRAM_CFG2_D_INIT 0x00000010 119 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 120 #define SDRAM_CFG2_ODT_NEVER 0 121 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 122 #define SDRAM_CFG2_ODT_ONLY_READ 2 123 #define SDRAM_CFG2_ODT_ALWAYS 3 124 125 #define TIMING_CFG_2_CPO_MASK 0x0F800000 126 127 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ 128 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) 129 #define RD_TO_PRE_MASK 0xf 130 #define RD_TO_PRE_SHIFT 13 131 #define WR_DATA_DELAY_MASK 0xf 132 #define WR_DATA_DELAY_SHIFT 9 133 #else 134 #define RD_TO_PRE_MASK 0x7 135 #define RD_TO_PRE_SHIFT 13 136 #define WR_DATA_DELAY_MASK 0x7 137 #define WR_DATA_DELAY_SHIFT 10 138 #endif 139 140 /* DDR_MD_CNTL */ 141 #define MD_CNTL_MD_EN 0x80000000 142 #define MD_CNTL_CS_SEL_CS0 0x00000000 143 #define MD_CNTL_CS_SEL_CS1 0x10000000 144 #define MD_CNTL_CS_SEL_CS2 0x20000000 145 #define MD_CNTL_CS_SEL_CS3 0x30000000 146 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 147 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 148 #define MD_CNTL_MD_SEL_MR 0x00000000 149 #define MD_CNTL_MD_SEL_EMR 0x01000000 150 #define MD_CNTL_MD_SEL_EMR2 0x02000000 151 #define MD_CNTL_MD_SEL_EMR3 0x03000000 152 #define MD_CNTL_SET_REF 0x00800000 153 #define MD_CNTL_SET_PRE 0x00400000 154 #define MD_CNTL_CKE_CNTL_LOW 0x00100000 155 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 156 #define MD_CNTL_WRCW 0x00080000 157 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) 158 159 /* DDR_CDR1 */ 160 #define DDR_CDR1_DHC_EN 0x80000000 161 #define DDR_CDR1_ODT_SHIFT 17 162 #define DDR_CDR1_ODT_MASK 0x6 163 #define DDR_CDR2_ODT_MASK 0x1 164 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) 165 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) 166 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) 167 168 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ 169 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) 170 #ifdef CONFIG_SYS_FSL_DDR3L 171 #define DDR_CDR_ODT_OFF 0x0 172 #define DDR_CDR_ODT_120ohm 0x1 173 #define DDR_CDR_ODT_200ohm 0x2 174 #define DDR_CDR_ODT_75ohm 0x3 175 #define DDR_CDR_ODT_60ohm 0x5 176 #define DDR_CDR_ODT_46ohm 0x7 177 #elif defined(CONFIG_SYS_FSL_DDR4) 178 #define DDR_CDR_ODT_OFF 0x0 179 #define DDR_CDR_ODT_100ohm 0x1 180 #define DDR_CDR_ODT_120OHM 0x2 181 #define DDR_CDR_ODT_80ohm 0x3 182 #define DDR_CDR_ODT_60ohm 0x4 183 #define DDR_CDR_ODT_40ohm 0x5 184 #define DDR_CDR_ODT_50ohm 0x6 185 #define DDR_CDR_ODT_30ohm 0x7 186 #else 187 #define DDR_CDR_ODT_OFF 0x0 188 #define DDR_CDR_ODT_120ohm 0x1 189 #define DDR_CDR_ODT_180ohm 0x2 190 #define DDR_CDR_ODT_75ohm 0x3 191 #define DDR_CDR_ODT_110ohm 0x4 192 #define DDR_CDR_ODT_60hm 0x5 193 #define DDR_CDR_ODT_70ohm 0x6 194 #define DDR_CDR_ODT_47ohm 0x7 195 #endif /* DDR3L */ 196 #else 197 #define DDR_CDR_ODT_75ohm 0x0 198 #define DDR_CDR_ODT_55ohm 0x1 199 #define DDR_CDR_ODT_60ohm 0x2 200 #define DDR_CDR_ODT_50ohm 0x3 201 #define DDR_CDR_ODT_150ohm 0x4 202 #define DDR_CDR_ODT_43ohm 0x5 203 #define DDR_CDR_ODT_120ohm 0x6 204 #endif 205 206 /* Record of register values computed */ 207 typedef struct fsl_ddr_cfg_regs_s { 208 struct { 209 unsigned int bnds; 210 unsigned int config; 211 unsigned int config_2; 212 } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; 213 unsigned int timing_cfg_3; 214 unsigned int timing_cfg_0; 215 unsigned int timing_cfg_1; 216 unsigned int timing_cfg_2; 217 unsigned int ddr_sdram_cfg; 218 unsigned int ddr_sdram_cfg_2; 219 unsigned int ddr_sdram_cfg_3; 220 unsigned int ddr_sdram_mode; 221 unsigned int ddr_sdram_mode_2; 222 unsigned int ddr_sdram_mode_3; 223 unsigned int ddr_sdram_mode_4; 224 unsigned int ddr_sdram_mode_5; 225 unsigned int ddr_sdram_mode_6; 226 unsigned int ddr_sdram_mode_7; 227 unsigned int ddr_sdram_mode_8; 228 unsigned int ddr_sdram_mode_9; 229 unsigned int ddr_sdram_mode_10; 230 unsigned int ddr_sdram_mode_11; 231 unsigned int ddr_sdram_mode_12; 232 unsigned int ddr_sdram_mode_13; 233 unsigned int ddr_sdram_mode_14; 234 unsigned int ddr_sdram_mode_15; 235 unsigned int ddr_sdram_mode_16; 236 unsigned int ddr_sdram_md_cntl; 237 unsigned int ddr_sdram_interval; 238 unsigned int ddr_data_init; 239 unsigned int ddr_sdram_clk_cntl; 240 unsigned int ddr_init_addr; 241 unsigned int ddr_init_ext_addr; 242 unsigned int timing_cfg_4; 243 unsigned int timing_cfg_5; 244 unsigned int timing_cfg_6; 245 unsigned int timing_cfg_7; 246 unsigned int timing_cfg_8; 247 unsigned int timing_cfg_9; 248 unsigned int ddr_zq_cntl; 249 unsigned int ddr_wrlvl_cntl; 250 unsigned int ddr_wrlvl_cntl_2; 251 unsigned int ddr_wrlvl_cntl_3; 252 unsigned int ddr_sr_cntr; 253 unsigned int ddr_sdram_rcw_1; 254 unsigned int ddr_sdram_rcw_2; 255 unsigned int ddr_sdram_rcw_3; 256 unsigned int ddr_sdram_rcw_4; 257 unsigned int ddr_sdram_rcw_5; 258 unsigned int ddr_sdram_rcw_6; 259 unsigned int dq_map_0; 260 unsigned int dq_map_1; 261 unsigned int dq_map_2; 262 unsigned int dq_map_3; 263 unsigned int ddr_eor; 264 unsigned int ddr_cdr1; 265 unsigned int ddr_cdr2; 266 unsigned int err_disable; 267 unsigned int err_int_en; 268 unsigned int debug[32]; 269 } fsl_ddr_cfg_regs_t; 270 271 typedef struct memctl_options_partial_s { 272 unsigned int all_dimms_ecc_capable; 273 unsigned int all_dimms_tckmax_ps; 274 unsigned int all_dimms_burst_lengths_bitmask; 275 unsigned int all_dimms_registered; 276 unsigned int all_dimms_unbuffered; 277 /* unsigned int lowest_common_spd_caslat; */ 278 unsigned int all_dimms_minimum_trcd_ps; 279 } memctl_options_partial_t; 280 281 #define DDR_DATA_BUS_WIDTH_64 0 282 #define DDR_DATA_BUS_WIDTH_32 1 283 #define DDR_DATA_BUS_WIDTH_16 2 284 /* 285 * Generalized parameters for memory controller configuration, 286 * might be a little specific to the FSL memory controller 287 */ 288 typedef struct memctl_options_s { 289 /* 290 * Memory organization parameters 291 * 292 * if DIMM is present in the system 293 * where DIMMs are with respect to chip select 294 * where chip selects are with respect to memory boundaries 295 */ 296 unsigned int registered_dimm_en; /* use registered DIMM support */ 297 298 /* Options local to a Chip Select */ 299 struct cs_local_opts_s { 300 unsigned int auto_precharge; 301 unsigned int odt_rd_cfg; 302 unsigned int odt_wr_cfg; 303 unsigned int odt_rtt_norm; 304 unsigned int odt_rtt_wr; 305 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; 306 307 /* Special configurations for chip select */ 308 unsigned int memctl_interleaving; 309 unsigned int memctl_interleaving_mode; 310 unsigned int ba_intlv_ctl; 311 unsigned int addr_hash; 312 313 /* Operational mode parameters */ 314 unsigned int ecc_mode; /* Use ECC? */ 315 /* Initialize ECC using memory controller? */ 316 unsigned int ecc_init_using_memctl; 317 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ 318 /* SREN - self-refresh during sleep */ 319 unsigned int self_refresh_in_sleep; 320 unsigned int dynamic_power; /* DYN_PWR */ 321 /* memory data width to use (16-bit, 32-bit, 64-bit) */ 322 unsigned int data_bus_width; 323 unsigned int burst_length; /* BL4, OTF and BL8 */ 324 /* On-The-Fly Burst Chop enable */ 325 unsigned int otf_burst_chop_en; 326 /* mirrior DIMMs for DDR3 */ 327 unsigned int mirrored_dimm; 328 unsigned int quad_rank_present; 329 unsigned int ap_en; /* address parity enable for RDIMM */ 330 unsigned int x4_en; /* enable x4 devices */ 331 332 /* Global Timing Parameters */ 333 unsigned int cas_latency_override; 334 unsigned int cas_latency_override_value; 335 unsigned int use_derated_caslat; 336 unsigned int additive_latency_override; 337 unsigned int additive_latency_override_value; 338 339 unsigned int clk_adjust; /* */ 340 unsigned int cpo_override; 341 unsigned int write_data_delay; /* DQS adjust */ 342 343 unsigned int wrlvl_override; 344 unsigned int wrlvl_sample; /* Write leveling */ 345 unsigned int wrlvl_start; 346 unsigned int wrlvl_ctl_2; 347 unsigned int wrlvl_ctl_3; 348 349 unsigned int half_strength_driver_enable; 350 unsigned int twot_en; 351 unsigned int threet_en; 352 unsigned int bstopre; 353 unsigned int tcke_clock_pulse_width_ps; /* tCKE */ 354 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ 355 356 /* Rtt impedance */ 357 unsigned int rtt_override; /* rtt_override enable */ 358 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ 359 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ 360 361 /* Automatic self refresh */ 362 unsigned int auto_self_refresh_en; 363 unsigned int sr_it; 364 /* ZQ calibration */ 365 unsigned int zq_en; 366 /* Write leveling */ 367 unsigned int wrlvl_en; 368 /* RCW override for RDIMM */ 369 unsigned int rcw_override; 370 unsigned int rcw_1; 371 unsigned int rcw_2; 372 /* control register 1 */ 373 unsigned int ddr_cdr1; 374 unsigned int ddr_cdr2; 375 376 unsigned int trwt_override; 377 unsigned int trwt; /* read-to-write turnaround */ 378 } memctl_options_t; 379 380 extern phys_size_t fsl_ddr_sdram(void); 381 extern phys_size_t fsl_ddr_sdram_size(void); 382 extern int fsl_use_spd(void); 383 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 384 unsigned int ctrl_num, int step); 385 u32 fsl_ddr_get_intl3r(void); 386 387 static void __board_assert_mem_reset(void) 388 { 389 } 390 391 static void __board_deassert_mem_reset(void) 392 { 393 } 394 395 void board_assert_mem_reset(void) 396 __attribute__((weak, alias("__board_assert_mem_reset"))); 397 398 void board_deassert_mem_reset(void) 399 __attribute__((weak, alias("__board_deassert_mem_reset"))); 400 401 static int __board_need_mem_reset(void) 402 { 403 return 0; 404 } 405 406 int board_need_mem_reset(void) 407 __attribute__((weak, alias("__board_need_mem_reset"))); 408 409 void __weak board_mem_sleep_setup(void) 410 { 411 } 412 413 /* 414 * The 85xx boards have a common prototype for fixed_sdram so put the 415 * declaration here. 416 */ 417 #ifdef CONFIG_MPC85xx 418 extern phys_size_t fixed_sdram(void); 419 #endif 420 421 #if defined(CONFIG_DDR_ECC) 422 extern void ddr_enable_ecc(unsigned int dram_size); 423 #endif 424 425 426 typedef struct fixed_ddr_parm{ 427 int min_freq; 428 int max_freq; 429 fsl_ddr_cfg_regs_t *ddr_settings; 430 } fixed_ddr_parm_t; 431 #endif 432