1 /* 2 * Copyright 2008-2016 Freescale Semiconductor, Inc. 3 * Copyright 2017-2018 NXP Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #ifndef FSL_DDR_MEMCTL_H 9 #define FSL_DDR_MEMCTL_H 10 11 /* 12 * Pick a basic DDR Technology. 13 */ 14 #include <ddr_spd.h> 15 #include <fsl_ddrc_version.h> 16 17 #define SDRAM_TYPE_DDR1 2 18 #define SDRAM_TYPE_DDR2 3 19 #define SDRAM_TYPE_LPDDR1 6 20 #define SDRAM_TYPE_DDR3 7 21 #define SDRAM_TYPE_DDR4 5 22 23 #define DDR_BL4 4 /* burst length 4 */ 24 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ 25 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 26 #define DDR_BL8 8 /* burst length 8 */ 27 28 #define DDR3_RTT_OFF 0 29 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ 30 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ 31 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ 32 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ 33 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ 34 35 #define DDR4_RTT_OFF 0 36 #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ 37 #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ 38 #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ 39 #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ 40 #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ 41 #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ 42 #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ 43 44 #define DDR2_RTT_OFF 0 45 #define DDR2_RTT_75_OHM 1 46 #define DDR2_RTT_150_OHM 2 47 #define DDR2_RTT_50_OHM 3 48 49 #if defined(CONFIG_SYS_FSL_DDR1) 50 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) 51 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; 52 #ifndef CONFIG_FSL_SDRAM_TYPE 53 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 54 #endif 55 #elif defined(CONFIG_SYS_FSL_DDR2) 56 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) 57 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; 58 #ifndef CONFIG_FSL_SDRAM_TYPE 59 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 60 #endif 61 #elif defined(CONFIG_SYS_FSL_DDR3) 62 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; 63 #ifndef CONFIG_FSL_SDRAM_TYPE 64 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 65 #endif 66 #elif defined(CONFIG_SYS_FSL_DDR4) 67 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ 68 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; 69 #ifndef CONFIG_FSL_SDRAM_TYPE 70 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 71 #endif 72 #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ 73 74 #define FSL_DDR_ODT_NEVER 0x0 75 #define FSL_DDR_ODT_CS 0x1 76 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2 77 #define FSL_DDR_ODT_OTHER_DIMM 0x3 78 #define FSL_DDR_ODT_ALL 0x4 79 #define FSL_DDR_ODT_SAME_DIMM 0x5 80 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 81 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 82 83 /* define bank(chip select) interleaving mode */ 84 #define FSL_DDR_CS0_CS1 0x40 85 #define FSL_DDR_CS2_CS3 0x20 86 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) 87 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) 88 89 /* define memory controller interleaving mode */ 90 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 91 #define FSL_DDR_PAGE_INTERLEAVING 0x1 92 #define FSL_DDR_BANK_INTERLEAVING 0x2 93 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 94 #define FSL_DDR_256B_INTERLEAVING 0x8 95 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA 96 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC 97 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD 98 /* placeholder for 4-way interleaving */ 99 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A 100 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C 101 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D 102 103 #define SDRAM_CS_CONFIG_EN 0x80000000 104 105 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 106 */ 107 #define SDRAM_CFG_MEM_EN 0x80000000 108 #define SDRAM_CFG_SREN 0x40000000 109 #define SDRAM_CFG_ECC_EN 0x20000000 110 #define SDRAM_CFG_RD_EN 0x10000000 111 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 112 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 113 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 114 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 115 #define SDRAM_CFG_DYN_PWR 0x00200000 116 #define SDRAM_CFG_DBW_MASK 0x00180000 117 #define SDRAM_CFG_DBW_SHIFT 19 118 #define SDRAM_CFG_32_BE 0x00080000 119 #define SDRAM_CFG_16_BE 0x00100000 120 #define SDRAM_CFG_8_BE 0x00040000 121 #define SDRAM_CFG_NCAP 0x00020000 122 #define SDRAM_CFG_2T_EN 0x00008000 123 #define SDRAM_CFG_BI 0x00000001 124 125 #define SDRAM_CFG2_FRC_SR 0x80000000 126 #define SDRAM_CFG2_D_INIT 0x00000010 127 #define SDRAM_CFG2_AP_EN 0x00000020 128 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 129 #define SDRAM_CFG2_ODT_NEVER 0 130 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 131 #define SDRAM_CFG2_ODT_ONLY_READ 2 132 #define SDRAM_CFG2_ODT_ALWAYS 3 133 134 #define SDRAM_INTERVAL_BSTOPRE 0x3FFF 135 #define TIMING_CFG_2_CPO_MASK 0x0F800000 136 137 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ 138 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) 139 #define RD_TO_PRE_MASK 0xf 140 #define RD_TO_PRE_SHIFT 13 141 #define WR_DATA_DELAY_MASK 0xf 142 #define WR_DATA_DELAY_SHIFT 9 143 #else 144 #define RD_TO_PRE_MASK 0x7 145 #define RD_TO_PRE_SHIFT 13 146 #define WR_DATA_DELAY_MASK 0x7 147 #define WR_DATA_DELAY_SHIFT 10 148 #endif 149 150 /* DDR_EOR register */ 151 #define DDR_EOR_RD_REOD_DIS 0x07000000 152 #define DDR_EOR_WD_REOD_DIS 0x00100000 153 154 /* DDR_MD_CNTL */ 155 #define MD_CNTL_MD_EN 0x80000000 156 #define MD_CNTL_CS_SEL_CS0 0x00000000 157 #define MD_CNTL_CS_SEL_CS1 0x10000000 158 #define MD_CNTL_CS_SEL_CS2 0x20000000 159 #define MD_CNTL_CS_SEL_CS3 0x30000000 160 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 161 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 162 #define MD_CNTL_MD_SEL_MR 0x00000000 163 #define MD_CNTL_MD_SEL_EMR 0x01000000 164 #define MD_CNTL_MD_SEL_EMR2 0x02000000 165 #define MD_CNTL_MD_SEL_EMR3 0x03000000 166 #define MD_CNTL_SET_REF 0x00800000 167 #define MD_CNTL_SET_PRE 0x00400000 168 #define MD_CNTL_CKE_CNTL_LOW 0x00100000 169 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 170 #define MD_CNTL_WRCW 0x00080000 171 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) 172 #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) 173 #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) 174 175 /* DDR_CDR1 */ 176 #define DDR_CDR1_DHC_EN 0x80000000 177 #define DDR_CDR1_V0PT9_EN 0x40000000 178 #define DDR_CDR1_ODT_SHIFT 17 179 #define DDR_CDR1_ODT_MASK 0x6 180 #define DDR_CDR2_ODT_MASK 0x1 181 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) 182 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) 183 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) 184 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 185 #define DDR_CDR2_VREF_RANGE_2 0x00000040 186 187 /* DDR ERR_DISABLE */ 188 #define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ 189 190 /* Mode Registers */ 191 #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ 192 #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ 193 194 /* DEBUG_26 register */ 195 #define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ 196 #define DDR_CAS_TO_PRE_SUB_SHIFT 12 197 198 /* DEBUG_29 register */ 199 #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ 200 201 202 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ 203 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) 204 #ifdef CONFIG_SYS_FSL_DDR3L 205 #define DDR_CDR_ODT_OFF 0x0 206 #define DDR_CDR_ODT_120ohm 0x1 207 #define DDR_CDR_ODT_200ohm 0x2 208 #define DDR_CDR_ODT_75ohm 0x3 209 #define DDR_CDR_ODT_60ohm 0x5 210 #define DDR_CDR_ODT_46ohm 0x7 211 #elif defined(CONFIG_SYS_FSL_DDR4) 212 #define DDR_CDR_ODT_OFF 0x0 213 #define DDR_CDR_ODT_100ohm 0x1 214 #define DDR_CDR_ODT_120OHM 0x2 215 #define DDR_CDR_ODT_80ohm 0x3 216 #define DDR_CDR_ODT_60ohm 0x4 217 #define DDR_CDR_ODT_40ohm 0x5 218 #define DDR_CDR_ODT_50ohm 0x6 219 #define DDR_CDR_ODT_30ohm 0x7 220 #else 221 #define DDR_CDR_ODT_OFF 0x0 222 #define DDR_CDR_ODT_120ohm 0x1 223 #define DDR_CDR_ODT_180ohm 0x2 224 #define DDR_CDR_ODT_75ohm 0x3 225 #define DDR_CDR_ODT_110ohm 0x4 226 #define DDR_CDR_ODT_60hm 0x5 227 #define DDR_CDR_ODT_70ohm 0x6 228 #define DDR_CDR_ODT_47ohm 0x7 229 #endif /* DDR3L */ 230 #else 231 #define DDR_CDR_ODT_75ohm 0x0 232 #define DDR_CDR_ODT_55ohm 0x1 233 #define DDR_CDR_ODT_60ohm 0x2 234 #define DDR_CDR_ODT_50ohm 0x3 235 #define DDR_CDR_ODT_150ohm 0x4 236 #define DDR_CDR_ODT_43ohm 0x5 237 #define DDR_CDR_ODT_120ohm 0x6 238 #endif 239 240 #define DDR_INIT_ADDR_EXT_UIA (1 << 31) 241 242 /* Record of register values computed */ 243 typedef struct fsl_ddr_cfg_regs_s { 244 struct { 245 unsigned int bnds; 246 unsigned int config; 247 unsigned int config_2; 248 } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; 249 unsigned int timing_cfg_3; 250 unsigned int timing_cfg_0; 251 unsigned int timing_cfg_1; 252 unsigned int timing_cfg_2; 253 unsigned int ddr_sdram_cfg; 254 unsigned int ddr_sdram_cfg_2; 255 unsigned int ddr_sdram_cfg_3; 256 unsigned int ddr_sdram_mode; 257 unsigned int ddr_sdram_mode_2; 258 unsigned int ddr_sdram_mode_3; 259 unsigned int ddr_sdram_mode_4; 260 unsigned int ddr_sdram_mode_5; 261 unsigned int ddr_sdram_mode_6; 262 unsigned int ddr_sdram_mode_7; 263 unsigned int ddr_sdram_mode_8; 264 unsigned int ddr_sdram_mode_9; 265 unsigned int ddr_sdram_mode_10; 266 unsigned int ddr_sdram_mode_11; 267 unsigned int ddr_sdram_mode_12; 268 unsigned int ddr_sdram_mode_13; 269 unsigned int ddr_sdram_mode_14; 270 unsigned int ddr_sdram_mode_15; 271 unsigned int ddr_sdram_mode_16; 272 unsigned int ddr_sdram_md_cntl; 273 unsigned int ddr_sdram_interval; 274 unsigned int ddr_data_init; 275 unsigned int ddr_sdram_clk_cntl; 276 unsigned int ddr_init_addr; 277 unsigned int ddr_init_ext_addr; 278 unsigned int timing_cfg_4; 279 unsigned int timing_cfg_5; 280 unsigned int timing_cfg_6; 281 unsigned int timing_cfg_7; 282 unsigned int timing_cfg_8; 283 unsigned int timing_cfg_9; 284 unsigned int ddr_zq_cntl; 285 unsigned int ddr_wrlvl_cntl; 286 unsigned int ddr_wrlvl_cntl_2; 287 unsigned int ddr_wrlvl_cntl_3; 288 unsigned int ddr_sr_cntr; 289 unsigned int ddr_sdram_rcw_1; 290 unsigned int ddr_sdram_rcw_2; 291 unsigned int ddr_sdram_rcw_3; 292 unsigned int ddr_sdram_rcw_4; 293 unsigned int ddr_sdram_rcw_5; 294 unsigned int ddr_sdram_rcw_6; 295 unsigned int dq_map_0; 296 unsigned int dq_map_1; 297 unsigned int dq_map_2; 298 unsigned int dq_map_3; 299 unsigned int ddr_eor; 300 unsigned int ddr_cdr1; 301 unsigned int ddr_cdr2; 302 unsigned int err_disable; 303 unsigned int err_int_en; 304 unsigned int debug[64]; 305 } fsl_ddr_cfg_regs_t; 306 307 typedef struct memctl_options_partial_s { 308 unsigned int all_dimms_ecc_capable; 309 unsigned int all_dimms_tckmax_ps; 310 unsigned int all_dimms_burst_lengths_bitmask; 311 unsigned int all_dimms_registered; 312 unsigned int all_dimms_unbuffered; 313 /* unsigned int lowest_common_spd_caslat; */ 314 unsigned int all_dimms_minimum_trcd_ps; 315 } memctl_options_partial_t; 316 317 #define DDR_DATA_BUS_WIDTH_64 0 318 #define DDR_DATA_BUS_WIDTH_32 1 319 #define DDR_DATA_BUS_WIDTH_16 2 320 #define DDR_CSWL_CS0 0x04000001 321 /* 322 * Generalized parameters for memory controller configuration, 323 * might be a little specific to the FSL memory controller 324 */ 325 typedef struct memctl_options_s { 326 /* 327 * Memory organization parameters 328 * 329 * if DIMM is present in the system 330 * where DIMMs are with respect to chip select 331 * where chip selects are with respect to memory boundaries 332 */ 333 unsigned int registered_dimm_en; /* use registered DIMM support */ 334 335 /* Options local to a Chip Select */ 336 struct cs_local_opts_s { 337 unsigned int auto_precharge; 338 unsigned int odt_rd_cfg; 339 unsigned int odt_wr_cfg; 340 unsigned int odt_rtt_norm; 341 unsigned int odt_rtt_wr; 342 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; 343 344 /* Special configurations for chip select */ 345 unsigned int memctl_interleaving; 346 unsigned int memctl_interleaving_mode; 347 unsigned int ba_intlv_ctl; 348 unsigned int addr_hash; 349 350 /* Operational mode parameters */ 351 unsigned int ecc_mode; /* Use ECC? */ 352 /* Initialize ECC using memory controller? */ 353 unsigned int ecc_init_using_memctl; 354 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ 355 /* SREN - self-refresh during sleep */ 356 unsigned int self_refresh_in_sleep; 357 /* SR_IE - Self-refresh interrupt enable */ 358 unsigned int self_refresh_interrupt_en; 359 unsigned int dynamic_power; /* DYN_PWR */ 360 /* memory data width to use (16-bit, 32-bit, 64-bit) */ 361 unsigned int data_bus_width; 362 unsigned int burst_length; /* BL4, OTF and BL8 */ 363 /* On-The-Fly Burst Chop enable */ 364 unsigned int otf_burst_chop_en; 365 /* mirrior DIMMs for DDR3 */ 366 unsigned int mirrored_dimm; 367 unsigned int quad_rank_present; 368 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ 369 unsigned int x4_en; /* enable x4 devices */ 370 unsigned int package_3ds; 371 372 /* Global Timing Parameters */ 373 unsigned int cas_latency_override; 374 unsigned int cas_latency_override_value; 375 unsigned int use_derated_caslat; 376 unsigned int additive_latency_override; 377 unsigned int additive_latency_override_value; 378 379 unsigned int clk_adjust; /* */ 380 unsigned int cpo_override; /* override timing_cfg_2[CPO]*/ 381 unsigned int cpo_sample; /* optimize debug_29[24:31] */ 382 unsigned int write_data_delay; /* DQS adjust */ 383 384 unsigned int cswl_override; 385 unsigned int wrlvl_override; 386 unsigned int wrlvl_sample; /* Write leveling */ 387 unsigned int wrlvl_start; 388 unsigned int wrlvl_ctl_2; 389 unsigned int wrlvl_ctl_3; 390 391 unsigned int half_strength_driver_enable; 392 unsigned int twot_en; 393 unsigned int threet_en; 394 unsigned int bstopre; 395 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ 396 397 /* Rtt impedance */ 398 unsigned int rtt_override; /* rtt_override enable */ 399 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ 400 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ 401 402 /* Automatic self refresh */ 403 unsigned int auto_self_refresh_en; 404 unsigned int sr_it; 405 /* ZQ calibration */ 406 unsigned int zq_en; 407 /* Write leveling */ 408 unsigned int wrlvl_en; 409 /* RCW override for RDIMM */ 410 unsigned int rcw_override; 411 unsigned int rcw_1; 412 unsigned int rcw_2; 413 unsigned int rcw_3; 414 /* control register 1 */ 415 unsigned int ddr_cdr1; 416 unsigned int ddr_cdr2; 417 418 unsigned int trwt_override; 419 unsigned int trwt; /* read-to-write turnaround */ 420 } memctl_options_t; 421 422 phys_size_t fsl_ddr_sdram(void); 423 phys_size_t fsl_ddr_sdram_size(void); 424 phys_size_t fsl_other_ddr_sdram(unsigned long long base, 425 unsigned int first_ctrl, 426 unsigned int num_ctrls, 427 unsigned int dimm_slots_per_ctrl, 428 int (*board_need_reset)(void), 429 void (*board_reset)(void), 430 void (*board_de_reset)(void)); 431 extern int fsl_use_spd(void); 432 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 433 unsigned int ctrl_num, int step); 434 u32 fsl_ddr_get_intl3r(void); 435 void print_ddr_info(unsigned int start_ctrl); 436 437 static void __board_assert_mem_reset(void) 438 { 439 } 440 441 static void __board_deassert_mem_reset(void) 442 { 443 } 444 445 void board_assert_mem_reset(void) 446 __attribute__((weak, alias("__board_assert_mem_reset"))); 447 448 void board_deassert_mem_reset(void) 449 __attribute__((weak, alias("__board_deassert_mem_reset"))); 450 451 static int __board_need_mem_reset(void) 452 { 453 return 0; 454 } 455 456 int board_need_mem_reset(void) 457 __attribute__((weak, alias("__board_need_mem_reset"))); 458 459 #if defined(CONFIG_DEEP_SLEEP) 460 void board_mem_sleep_setup(void); 461 bool is_warm_boot(void); 462 int fsl_dp_resume(void); 463 #endif 464 465 /* 466 * The 85xx boards have a common prototype for fixed_sdram so put the 467 * declaration here. 468 */ 469 #ifdef CONFIG_MPC85xx 470 extern phys_size_t fixed_sdram(void); 471 #endif 472 473 #if defined(CONFIG_DDR_ECC) 474 extern void ddr_enable_ecc(unsigned int dram_size); 475 #endif 476 477 478 typedef struct fixed_ddr_parm{ 479 int min_freq; 480 int max_freq; 481 fsl_ddr_cfg_regs_t *ddr_settings; 482 } fixed_ddr_parm_t; 483 484 /** 485 * fsl_initdram() - Set up the SDRAM 486 * 487 * @return 0 if OK, -ve on error 488 */ 489 int fsl_initdram(void); 490 491 #endif 492