1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef FSL_DDR_MEMCTL_H 10 #define FSL_DDR_MEMCTL_H 11 12 /* 13 * Pick a basic DDR Technology. 14 */ 15 #include <ddr_spd.h> 16 17 #define SDRAM_TYPE_DDR1 2 18 #define SDRAM_TYPE_DDR2 3 19 #define SDRAM_TYPE_LPDDR1 6 20 #define SDRAM_TYPE_DDR3 7 21 22 #define DDR_BL4 4 /* burst length 4 */ 23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ 24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 25 #define DDR_BL8 8 /* burst length 8 */ 26 27 #define DDR3_RTT_OFF 0 28 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ 29 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ 30 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ 31 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ 32 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ 33 34 #define DDR2_RTT_OFF 0 35 #define DDR2_RTT_75_OHM 1 36 #define DDR2_RTT_150_OHM 2 37 #define DDR2_RTT_50_OHM 3 38 39 #if defined(CONFIG_SYS_FSL_DDR1) 40 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) 41 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; 42 #ifndef CONFIG_FSL_SDRAM_TYPE 43 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 44 #endif 45 #elif defined(CONFIG_SYS_FSL_DDR2) 46 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) 47 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; 48 #ifndef CONFIG_FSL_SDRAM_TYPE 49 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 50 #endif 51 #elif defined(CONFIG_SYS_FSL_DDR3) 52 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ 53 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; 54 #ifndef CONFIG_FSL_SDRAM_TYPE 55 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 56 #endif 57 #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ 58 59 #define FSL_DDR_ODT_NEVER 0x0 60 #define FSL_DDR_ODT_CS 0x1 61 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2 62 #define FSL_DDR_ODT_OTHER_DIMM 0x3 63 #define FSL_DDR_ODT_ALL 0x4 64 #define FSL_DDR_ODT_SAME_DIMM 0x5 65 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 66 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 67 68 /* define bank(chip select) interleaving mode */ 69 #define FSL_DDR_CS0_CS1 0x40 70 #define FSL_DDR_CS2_CS3 0x20 71 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) 72 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) 73 74 /* define memory controller interleaving mode */ 75 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 76 #define FSL_DDR_PAGE_INTERLEAVING 0x1 77 #define FSL_DDR_BANK_INTERLEAVING 0x2 78 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 79 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA 80 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC 81 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD 82 /* placeholder for 4-way interleaving */ 83 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A 84 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C 85 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D 86 87 #define SDRAM_CS_CONFIG_EN 0x80000000 88 89 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 90 */ 91 #define SDRAM_CFG_MEM_EN 0x80000000 92 #define SDRAM_CFG_SREN 0x40000000 93 #define SDRAM_CFG_ECC_EN 0x20000000 94 #define SDRAM_CFG_RD_EN 0x10000000 95 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 96 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 97 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 98 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 99 #define SDRAM_CFG_DYN_PWR 0x00200000 100 #define SDRAM_CFG_DBW_MASK 0x00180000 101 #define SDRAM_CFG_DBW_SHIFT 19 102 #define SDRAM_CFG_32_BE 0x00080000 103 #define SDRAM_CFG_16_BE 0x00100000 104 #define SDRAM_CFG_8_BE 0x00040000 105 #define SDRAM_CFG_NCAP 0x00020000 106 #define SDRAM_CFG_2T_EN 0x00008000 107 #define SDRAM_CFG_BI 0x00000001 108 109 #define SDRAM_CFG2_D_INIT 0x00000010 110 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 111 #define SDRAM_CFG2_ODT_NEVER 0 112 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 113 #define SDRAM_CFG2_ODT_ONLY_READ 2 114 #define SDRAM_CFG2_ODT_ALWAYS 3 115 116 #define TIMING_CFG_2_CPO_MASK 0x0F800000 117 118 #if defined(CONFIG_P4080) 119 #define RD_TO_PRE_MASK 0xf 120 #define RD_TO_PRE_SHIFT 13 121 #define WR_DATA_DELAY_MASK 0xf 122 #define WR_DATA_DELAY_SHIFT 9 123 #else 124 #define RD_TO_PRE_MASK 0x7 125 #define RD_TO_PRE_SHIFT 13 126 #define WR_DATA_DELAY_MASK 0x7 127 #define WR_DATA_DELAY_SHIFT 10 128 #endif 129 130 /* DDR_MD_CNTL */ 131 #define MD_CNTL_MD_EN 0x80000000 132 #define MD_CNTL_CS_SEL_CS0 0x00000000 133 #define MD_CNTL_CS_SEL_CS1 0x10000000 134 #define MD_CNTL_CS_SEL_CS2 0x20000000 135 #define MD_CNTL_CS_SEL_CS3 0x30000000 136 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 137 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 138 #define MD_CNTL_MD_SEL_MR 0x00000000 139 #define MD_CNTL_MD_SEL_EMR 0x01000000 140 #define MD_CNTL_MD_SEL_EMR2 0x02000000 141 #define MD_CNTL_MD_SEL_EMR3 0x03000000 142 #define MD_CNTL_SET_REF 0x00800000 143 #define MD_CNTL_SET_PRE 0x00400000 144 #define MD_CNTL_CKE_CNTL_LOW 0x00100000 145 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 146 #define MD_CNTL_WRCW 0x00080000 147 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) 148 149 /* DDR_CDR1 */ 150 #define DDR_CDR1_DHC_EN 0x80000000 151 #define DDR_CDR1_ODT_SHIFT 17 152 #define DDR_CDR1_ODT_MASK 0x6 153 #define DDR_CDR2_ODT_MASK 0x1 154 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) 155 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) 156 157 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ 158 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) 159 #define DDR_CDR_ODT_OFF 0x0 160 #define DDR_CDR_ODT_120ohm 0x1 161 #define DDR_CDR_ODT_180ohm 0x2 162 #define DDR_CDR_ODT_75ohm 0x3 163 #define DDR_CDR_ODT_110ohm 0x4 164 #define DDR_CDR_ODT_60hm 0x5 165 #define DDR_CDR_ODT_70ohm 0x6 166 #define DDR_CDR_ODT_47ohm 0x7 167 #else 168 #define DDR_CDR_ODT_75ohm 0x0 169 #define DDR_CDR_ODT_55ohm 0x1 170 #define DDR_CDR_ODT_60ohm 0x2 171 #define DDR_CDR_ODT_50ohm 0x3 172 #define DDR_CDR_ODT_150ohm 0x4 173 #define DDR_CDR_ODT_43ohm 0x5 174 #define DDR_CDR_ODT_120ohm 0x6 175 #endif 176 177 /* Record of register values computed */ 178 typedef struct fsl_ddr_cfg_regs_s { 179 struct { 180 unsigned int bnds; 181 unsigned int config; 182 unsigned int config_2; 183 } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; 184 unsigned int timing_cfg_3; 185 unsigned int timing_cfg_0; 186 unsigned int timing_cfg_1; 187 unsigned int timing_cfg_2; 188 unsigned int ddr_sdram_cfg; 189 unsigned int ddr_sdram_cfg_2; 190 unsigned int ddr_sdram_mode; 191 unsigned int ddr_sdram_mode_2; 192 unsigned int ddr_sdram_mode_3; 193 unsigned int ddr_sdram_mode_4; 194 unsigned int ddr_sdram_mode_5; 195 unsigned int ddr_sdram_mode_6; 196 unsigned int ddr_sdram_mode_7; 197 unsigned int ddr_sdram_mode_8; 198 unsigned int ddr_sdram_md_cntl; 199 unsigned int ddr_sdram_interval; 200 unsigned int ddr_data_init; 201 unsigned int ddr_sdram_clk_cntl; 202 unsigned int ddr_init_addr; 203 unsigned int ddr_init_ext_addr; 204 unsigned int timing_cfg_4; 205 unsigned int timing_cfg_5; 206 unsigned int ddr_zq_cntl; 207 unsigned int ddr_wrlvl_cntl; 208 unsigned int ddr_wrlvl_cntl_2; 209 unsigned int ddr_wrlvl_cntl_3; 210 unsigned int ddr_sr_cntr; 211 unsigned int ddr_sdram_rcw_1; 212 unsigned int ddr_sdram_rcw_2; 213 unsigned int ddr_eor; 214 unsigned int ddr_cdr1; 215 unsigned int ddr_cdr2; 216 unsigned int err_disable; 217 unsigned int err_int_en; 218 unsigned int debug[32]; 219 } fsl_ddr_cfg_regs_t; 220 221 typedef struct memctl_options_partial_s { 222 unsigned int all_dimms_ecc_capable; 223 unsigned int all_dimms_tckmax_ps; 224 unsigned int all_dimms_burst_lengths_bitmask; 225 unsigned int all_dimms_registered; 226 unsigned int all_dimms_unbuffered; 227 /* unsigned int lowest_common_SPD_caslat; */ 228 unsigned int all_dimms_minimum_trcd_ps; 229 } memctl_options_partial_t; 230 231 #define DDR_DATA_BUS_WIDTH_64 0 232 #define DDR_DATA_BUS_WIDTH_32 1 233 #define DDR_DATA_BUS_WIDTH_16 2 234 /* 235 * Generalized parameters for memory controller configuration, 236 * might be a little specific to the FSL memory controller 237 */ 238 typedef struct memctl_options_s { 239 /* 240 * Memory organization parameters 241 * 242 * if DIMM is present in the system 243 * where DIMMs are with respect to chip select 244 * where chip selects are with respect to memory boundaries 245 */ 246 unsigned int registered_dimm_en; /* use registered DIMM support */ 247 248 /* Options local to a Chip Select */ 249 struct cs_local_opts_s { 250 unsigned int auto_precharge; 251 unsigned int odt_rd_cfg; 252 unsigned int odt_wr_cfg; 253 unsigned int odt_rtt_norm; 254 unsigned int odt_rtt_wr; 255 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; 256 257 /* Special configurations for chip select */ 258 unsigned int memctl_interleaving; 259 unsigned int memctl_interleaving_mode; 260 unsigned int ba_intlv_ctl; 261 unsigned int addr_hash; 262 263 /* Operational mode parameters */ 264 unsigned int ecc_mode; /* Use ECC? */ 265 /* Initialize ECC using memory controller? */ 266 unsigned int ecc_init_using_memctl; 267 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ 268 /* SREN - self-refresh during sleep */ 269 unsigned int self_refresh_in_sleep; 270 unsigned int dynamic_power; /* DYN_PWR */ 271 /* memory data width to use (16-bit, 32-bit, 64-bit) */ 272 unsigned int data_bus_width; 273 unsigned int burst_length; /* BL4, OTF and BL8 */ 274 /* On-The-Fly Burst Chop enable */ 275 unsigned int otf_burst_chop_en; 276 /* mirrior DIMMs for DDR3 */ 277 unsigned int mirrored_dimm; 278 unsigned int quad_rank_present; 279 unsigned int ap_en; /* address parity enable for RDIMM */ 280 unsigned int x4_en; /* enable x4 devices */ 281 282 /* Global Timing Parameters */ 283 unsigned int cas_latency_override; 284 unsigned int cas_latency_override_value; 285 unsigned int use_derated_caslat; 286 unsigned int additive_latency_override; 287 unsigned int additive_latency_override_value; 288 289 unsigned int clk_adjust; /* */ 290 unsigned int cpo_override; 291 unsigned int write_data_delay; /* DQS adjust */ 292 293 unsigned int wrlvl_override; 294 unsigned int wrlvl_sample; /* Write leveling */ 295 unsigned int wrlvl_start; 296 unsigned int wrlvl_ctl_2; 297 unsigned int wrlvl_ctl_3; 298 299 unsigned int half_strength_driver_enable; 300 unsigned int twot_en; 301 unsigned int threet_en; 302 unsigned int bstopre; 303 unsigned int tcke_clock_pulse_width_ps; /* tCKE */ 304 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ 305 306 /* Rtt impedance */ 307 unsigned int rtt_override; /* rtt_override enable */ 308 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ 309 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ 310 311 /* Automatic self refresh */ 312 unsigned int auto_self_refresh_en; 313 unsigned int sr_it; 314 /* ZQ calibration */ 315 unsigned int zq_en; 316 /* Write leveling */ 317 unsigned int wrlvl_en; 318 /* RCW override for RDIMM */ 319 unsigned int rcw_override; 320 unsigned int rcw_1; 321 unsigned int rcw_2; 322 /* control register 1 */ 323 unsigned int ddr_cdr1; 324 unsigned int ddr_cdr2; 325 326 unsigned int trwt_override; 327 unsigned int trwt; /* read-to-write turnaround */ 328 } memctl_options_t; 329 330 extern phys_size_t fsl_ddr_sdram(void); 331 extern phys_size_t fsl_ddr_sdram_size(void); 332 extern int fsl_use_spd(void); 333 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 334 unsigned int ctrl_num, int step); 335 u32 fsl_ddr_get_intl3r(void); 336 337 static void __board_assert_mem_reset(void) 338 { 339 } 340 341 static void __board_deassert_mem_reset(void) 342 { 343 } 344 345 void board_assert_mem_reset(void) 346 __attribute__((weak, alias("__board_assert_mem_reset"))); 347 348 void board_deassert_mem_reset(void) 349 __attribute__((weak, alias("__board_deassert_mem_reset"))); 350 351 static int __board_need_mem_reset(void) 352 { 353 return 0; 354 } 355 356 int board_need_mem_reset(void) 357 __attribute__((weak, alias("__board_need_mem_reset"))); 358 359 /* 360 * The 85xx boards have a common prototype for fixed_sdram so put the 361 * declaration here. 362 */ 363 #ifdef CONFIG_MPC85xx 364 extern phys_size_t fixed_sdram(void); 365 #endif 366 367 #if defined(CONFIG_DDR_ECC) 368 extern void ddr_enable_ecc(unsigned int dram_size); 369 #endif 370 371 372 typedef struct fixed_ddr_parm{ 373 int min_freq; 374 int max_freq; 375 fsl_ddr_cfg_regs_t *ddr_settings; 376 } fixed_ddr_parm_t; 377 #endif 378