1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef FSL_DDR_MEMCTL_H 8 #define FSL_DDR_MEMCTL_H 9 10 /* 11 * Pick a basic DDR Technology. 12 */ 13 #include <ddr_spd.h> 14 #include <fsl_ddrc_version.h> 15 16 #define SDRAM_TYPE_DDR1 2 17 #define SDRAM_TYPE_DDR2 3 18 #define SDRAM_TYPE_LPDDR1 6 19 #define SDRAM_TYPE_DDR3 7 20 #define SDRAM_TYPE_DDR4 5 21 22 #define DDR_BL4 4 /* burst length 4 */ 23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ 24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 25 #define DDR_BL8 8 /* burst length 8 */ 26 27 #define DDR3_RTT_OFF 0 28 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ 29 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ 30 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ 31 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ 32 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ 33 34 #define DDR4_RTT_OFF 0 35 #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ 36 #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ 37 #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ 38 #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ 39 #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ 40 #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ 41 #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ 42 43 #define DDR2_RTT_OFF 0 44 #define DDR2_RTT_75_OHM 1 45 #define DDR2_RTT_150_OHM 2 46 #define DDR2_RTT_50_OHM 3 47 48 #if defined(CONFIG_SYS_FSL_DDR1) 49 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) 50 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; 51 #ifndef CONFIG_FSL_SDRAM_TYPE 52 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 53 #endif 54 #elif defined(CONFIG_SYS_FSL_DDR2) 55 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) 56 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; 57 #ifndef CONFIG_FSL_SDRAM_TYPE 58 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 59 #endif 60 #elif defined(CONFIG_SYS_FSL_DDR3) 61 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; 62 #ifndef CONFIG_FSL_SDRAM_TYPE 63 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 64 #endif 65 #elif defined(CONFIG_SYS_FSL_DDR4) 66 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ 67 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; 68 #ifndef CONFIG_FSL_SDRAM_TYPE 69 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 70 #endif 71 #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ 72 73 #define FSL_DDR_ODT_NEVER 0x0 74 #define FSL_DDR_ODT_CS 0x1 75 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2 76 #define FSL_DDR_ODT_OTHER_DIMM 0x3 77 #define FSL_DDR_ODT_ALL 0x4 78 #define FSL_DDR_ODT_SAME_DIMM 0x5 79 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 80 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 81 82 /* define bank(chip select) interleaving mode */ 83 #define FSL_DDR_CS0_CS1 0x40 84 #define FSL_DDR_CS2_CS3 0x20 85 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) 86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) 87 88 /* define memory controller interleaving mode */ 89 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 90 #define FSL_DDR_PAGE_INTERLEAVING 0x1 91 #define FSL_DDR_BANK_INTERLEAVING 0x2 92 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 93 #define FSL_DDR_256B_INTERLEAVING 0x8 94 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA 95 #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC 96 #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD 97 /* placeholder for 4-way interleaving */ 98 #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A 99 #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C 100 #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D 101 102 #define SDRAM_CS_CONFIG_EN 0x80000000 103 104 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 105 */ 106 #define SDRAM_CFG_MEM_EN 0x80000000 107 #define SDRAM_CFG_SREN 0x40000000 108 #define SDRAM_CFG_ECC_EN 0x20000000 109 #define SDRAM_CFG_RD_EN 0x10000000 110 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 111 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 112 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 113 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 114 #define SDRAM_CFG_DYN_PWR 0x00200000 115 #define SDRAM_CFG_DBW_MASK 0x00180000 116 #define SDRAM_CFG_DBW_SHIFT 19 117 #define SDRAM_CFG_32_BE 0x00080000 118 #define SDRAM_CFG_16_BE 0x00100000 119 #define SDRAM_CFG_8_BE 0x00040000 120 #define SDRAM_CFG_NCAP 0x00020000 121 #define SDRAM_CFG_2T_EN 0x00008000 122 #define SDRAM_CFG_BI 0x00000001 123 124 #define SDRAM_CFG2_FRC_SR 0x80000000 125 #define SDRAM_CFG2_D_INIT 0x00000010 126 #define SDRAM_CFG2_AP_EN 0x00000020 127 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 128 #define SDRAM_CFG2_ODT_NEVER 0 129 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 130 #define SDRAM_CFG2_ODT_ONLY_READ 2 131 #define SDRAM_CFG2_ODT_ALWAYS 3 132 133 #define SDRAM_INTERVAL_BSTOPRE 0x3FFF 134 #define TIMING_CFG_2_CPO_MASK 0x0F800000 135 136 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ 137 (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) 138 #define RD_TO_PRE_MASK 0xf 139 #define RD_TO_PRE_SHIFT 13 140 #define WR_DATA_DELAY_MASK 0xf 141 #define WR_DATA_DELAY_SHIFT 9 142 #else 143 #define RD_TO_PRE_MASK 0x7 144 #define RD_TO_PRE_SHIFT 13 145 #define WR_DATA_DELAY_MASK 0x7 146 #define WR_DATA_DELAY_SHIFT 10 147 #endif 148 149 /* DDR_MD_CNTL */ 150 #define MD_CNTL_MD_EN 0x80000000 151 #define MD_CNTL_CS_SEL_CS0 0x00000000 152 #define MD_CNTL_CS_SEL_CS1 0x10000000 153 #define MD_CNTL_CS_SEL_CS2 0x20000000 154 #define MD_CNTL_CS_SEL_CS3 0x30000000 155 #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 156 #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 157 #define MD_CNTL_MD_SEL_MR 0x00000000 158 #define MD_CNTL_MD_SEL_EMR 0x01000000 159 #define MD_CNTL_MD_SEL_EMR2 0x02000000 160 #define MD_CNTL_MD_SEL_EMR3 0x03000000 161 #define MD_CNTL_SET_REF 0x00800000 162 #define MD_CNTL_SET_PRE 0x00400000 163 #define MD_CNTL_CKE_CNTL_LOW 0x00100000 164 #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 165 #define MD_CNTL_WRCW 0x00080000 166 #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) 167 #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) 168 #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) 169 170 /* DDR_CDR1 */ 171 #define DDR_CDR1_DHC_EN 0x80000000 172 #define DDR_CDR1_ODT_SHIFT 17 173 #define DDR_CDR1_ODT_MASK 0x6 174 #define DDR_CDR2_ODT_MASK 0x1 175 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) 176 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) 177 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) 178 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 179 #define DDR_CDR2_VREF_RANGE_2 0x00000040 180 181 /* DDR ERR_DISABLE */ 182 #define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ 183 184 /* Mode Registers */ 185 #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ 186 #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ 187 188 189 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ 190 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) 191 #ifdef CONFIG_SYS_FSL_DDR3L 192 #define DDR_CDR_ODT_OFF 0x0 193 #define DDR_CDR_ODT_120ohm 0x1 194 #define DDR_CDR_ODT_200ohm 0x2 195 #define DDR_CDR_ODT_75ohm 0x3 196 #define DDR_CDR_ODT_60ohm 0x5 197 #define DDR_CDR_ODT_46ohm 0x7 198 #elif defined(CONFIG_SYS_FSL_DDR4) 199 #define DDR_CDR_ODT_OFF 0x0 200 #define DDR_CDR_ODT_100ohm 0x1 201 #define DDR_CDR_ODT_120OHM 0x2 202 #define DDR_CDR_ODT_80ohm 0x3 203 #define DDR_CDR_ODT_60ohm 0x4 204 #define DDR_CDR_ODT_40ohm 0x5 205 #define DDR_CDR_ODT_50ohm 0x6 206 #define DDR_CDR_ODT_30ohm 0x7 207 #else 208 #define DDR_CDR_ODT_OFF 0x0 209 #define DDR_CDR_ODT_120ohm 0x1 210 #define DDR_CDR_ODT_180ohm 0x2 211 #define DDR_CDR_ODT_75ohm 0x3 212 #define DDR_CDR_ODT_110ohm 0x4 213 #define DDR_CDR_ODT_60hm 0x5 214 #define DDR_CDR_ODT_70ohm 0x6 215 #define DDR_CDR_ODT_47ohm 0x7 216 #endif /* DDR3L */ 217 #else 218 #define DDR_CDR_ODT_75ohm 0x0 219 #define DDR_CDR_ODT_55ohm 0x1 220 #define DDR_CDR_ODT_60ohm 0x2 221 #define DDR_CDR_ODT_50ohm 0x3 222 #define DDR_CDR_ODT_150ohm 0x4 223 #define DDR_CDR_ODT_43ohm 0x5 224 #define DDR_CDR_ODT_120ohm 0x6 225 #endif 226 227 #define DDR_INIT_ADDR_EXT_UIA (1 << 31) 228 229 /* Record of register values computed */ 230 typedef struct fsl_ddr_cfg_regs_s { 231 struct { 232 unsigned int bnds; 233 unsigned int config; 234 unsigned int config_2; 235 } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; 236 unsigned int timing_cfg_3; 237 unsigned int timing_cfg_0; 238 unsigned int timing_cfg_1; 239 unsigned int timing_cfg_2; 240 unsigned int ddr_sdram_cfg; 241 unsigned int ddr_sdram_cfg_2; 242 unsigned int ddr_sdram_cfg_3; 243 unsigned int ddr_sdram_mode; 244 unsigned int ddr_sdram_mode_2; 245 unsigned int ddr_sdram_mode_3; 246 unsigned int ddr_sdram_mode_4; 247 unsigned int ddr_sdram_mode_5; 248 unsigned int ddr_sdram_mode_6; 249 unsigned int ddr_sdram_mode_7; 250 unsigned int ddr_sdram_mode_8; 251 unsigned int ddr_sdram_mode_9; 252 unsigned int ddr_sdram_mode_10; 253 unsigned int ddr_sdram_mode_11; 254 unsigned int ddr_sdram_mode_12; 255 unsigned int ddr_sdram_mode_13; 256 unsigned int ddr_sdram_mode_14; 257 unsigned int ddr_sdram_mode_15; 258 unsigned int ddr_sdram_mode_16; 259 unsigned int ddr_sdram_md_cntl; 260 unsigned int ddr_sdram_interval; 261 unsigned int ddr_data_init; 262 unsigned int ddr_sdram_clk_cntl; 263 unsigned int ddr_init_addr; 264 unsigned int ddr_init_ext_addr; 265 unsigned int timing_cfg_4; 266 unsigned int timing_cfg_5; 267 unsigned int timing_cfg_6; 268 unsigned int timing_cfg_7; 269 unsigned int timing_cfg_8; 270 unsigned int timing_cfg_9; 271 unsigned int ddr_zq_cntl; 272 unsigned int ddr_wrlvl_cntl; 273 unsigned int ddr_wrlvl_cntl_2; 274 unsigned int ddr_wrlvl_cntl_3; 275 unsigned int ddr_sr_cntr; 276 unsigned int ddr_sdram_rcw_1; 277 unsigned int ddr_sdram_rcw_2; 278 unsigned int ddr_sdram_rcw_3; 279 unsigned int ddr_sdram_rcw_4; 280 unsigned int ddr_sdram_rcw_5; 281 unsigned int ddr_sdram_rcw_6; 282 unsigned int dq_map_0; 283 unsigned int dq_map_1; 284 unsigned int dq_map_2; 285 unsigned int dq_map_3; 286 unsigned int ddr_eor; 287 unsigned int ddr_cdr1; 288 unsigned int ddr_cdr2; 289 unsigned int err_disable; 290 unsigned int err_int_en; 291 unsigned int debug[32]; 292 } fsl_ddr_cfg_regs_t; 293 294 typedef struct memctl_options_partial_s { 295 unsigned int all_dimms_ecc_capable; 296 unsigned int all_dimms_tckmax_ps; 297 unsigned int all_dimms_burst_lengths_bitmask; 298 unsigned int all_dimms_registered; 299 unsigned int all_dimms_unbuffered; 300 /* unsigned int lowest_common_spd_caslat; */ 301 unsigned int all_dimms_minimum_trcd_ps; 302 } memctl_options_partial_t; 303 304 #define DDR_DATA_BUS_WIDTH_64 0 305 #define DDR_DATA_BUS_WIDTH_32 1 306 #define DDR_DATA_BUS_WIDTH_16 2 307 #define DDR_CSWL_CS0 0x04000001 308 /* 309 * Generalized parameters for memory controller configuration, 310 * might be a little specific to the FSL memory controller 311 */ 312 typedef struct memctl_options_s { 313 /* 314 * Memory organization parameters 315 * 316 * if DIMM is present in the system 317 * where DIMMs are with respect to chip select 318 * where chip selects are with respect to memory boundaries 319 */ 320 unsigned int registered_dimm_en; /* use registered DIMM support */ 321 322 /* Options local to a Chip Select */ 323 struct cs_local_opts_s { 324 unsigned int auto_precharge; 325 unsigned int odt_rd_cfg; 326 unsigned int odt_wr_cfg; 327 unsigned int odt_rtt_norm; 328 unsigned int odt_rtt_wr; 329 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; 330 331 /* Special configurations for chip select */ 332 unsigned int memctl_interleaving; 333 unsigned int memctl_interleaving_mode; 334 unsigned int ba_intlv_ctl; 335 unsigned int addr_hash; 336 337 /* Operational mode parameters */ 338 unsigned int ecc_mode; /* Use ECC? */ 339 /* Initialize ECC using memory controller? */ 340 unsigned int ecc_init_using_memctl; 341 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ 342 /* SREN - self-refresh during sleep */ 343 unsigned int self_refresh_in_sleep; 344 /* SR_IE - Self-refresh interrupt enable */ 345 unsigned int self_refresh_interrupt_en; 346 unsigned int dynamic_power; /* DYN_PWR */ 347 /* memory data width to use (16-bit, 32-bit, 64-bit) */ 348 unsigned int data_bus_width; 349 unsigned int burst_length; /* BL4, OTF and BL8 */ 350 /* On-The-Fly Burst Chop enable */ 351 unsigned int otf_burst_chop_en; 352 /* mirrior DIMMs for DDR3 */ 353 unsigned int mirrored_dimm; 354 unsigned int quad_rank_present; 355 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ 356 unsigned int x4_en; /* enable x4 devices */ 357 358 /* Global Timing Parameters */ 359 unsigned int cas_latency_override; 360 unsigned int cas_latency_override_value; 361 unsigned int use_derated_caslat; 362 unsigned int additive_latency_override; 363 unsigned int additive_latency_override_value; 364 365 unsigned int clk_adjust; /* */ 366 unsigned int cpo_override; 367 unsigned int write_data_delay; /* DQS adjust */ 368 369 unsigned int cswl_override; 370 unsigned int wrlvl_override; 371 unsigned int wrlvl_sample; /* Write leveling */ 372 unsigned int wrlvl_start; 373 unsigned int wrlvl_ctl_2; 374 unsigned int wrlvl_ctl_3; 375 376 unsigned int half_strength_driver_enable; 377 unsigned int twot_en; 378 unsigned int threet_en; 379 unsigned int bstopre; 380 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ 381 382 /* Rtt impedance */ 383 unsigned int rtt_override; /* rtt_override enable */ 384 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ 385 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ 386 387 /* Automatic self refresh */ 388 unsigned int auto_self_refresh_en; 389 unsigned int sr_it; 390 /* ZQ calibration */ 391 unsigned int zq_en; 392 /* Write leveling */ 393 unsigned int wrlvl_en; 394 /* RCW override for RDIMM */ 395 unsigned int rcw_override; 396 unsigned int rcw_1; 397 unsigned int rcw_2; 398 /* control register 1 */ 399 unsigned int ddr_cdr1; 400 unsigned int ddr_cdr2; 401 402 unsigned int trwt_override; 403 unsigned int trwt; /* read-to-write turnaround */ 404 } memctl_options_t; 405 406 phys_size_t fsl_ddr_sdram(void); 407 phys_size_t fsl_ddr_sdram_size(void); 408 phys_size_t fsl_other_ddr_sdram(unsigned long long base, 409 unsigned int first_ctrl, 410 unsigned int num_ctrls, 411 unsigned int dimm_slots_per_ctrl, 412 int (*board_need_reset)(void), 413 void (*board_reset)(void), 414 void (*board_de_reset)(void)); 415 extern int fsl_use_spd(void); 416 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 417 unsigned int ctrl_num, int step); 418 u32 fsl_ddr_get_intl3r(void); 419 void print_ddr_info(unsigned int start_ctrl); 420 421 static void __board_assert_mem_reset(void) 422 { 423 } 424 425 static void __board_deassert_mem_reset(void) 426 { 427 } 428 429 void board_assert_mem_reset(void) 430 __attribute__((weak, alias("__board_assert_mem_reset"))); 431 432 void board_deassert_mem_reset(void) 433 __attribute__((weak, alias("__board_deassert_mem_reset"))); 434 435 static int __board_need_mem_reset(void) 436 { 437 return 0; 438 } 439 440 int board_need_mem_reset(void) 441 __attribute__((weak, alias("__board_need_mem_reset"))); 442 443 #if defined(CONFIG_DEEP_SLEEP) 444 void board_mem_sleep_setup(void); 445 bool is_warm_boot(void); 446 int fsl_dp_resume(void); 447 #endif 448 449 /* 450 * The 85xx boards have a common prototype for fixed_sdram so put the 451 * declaration here. 452 */ 453 #ifdef CONFIG_MPC85xx 454 extern phys_size_t fixed_sdram(void); 455 #endif 456 457 #if defined(CONFIG_DDR_ECC) 458 extern void ddr_enable_ecc(unsigned int dram_size); 459 #endif 460 461 462 typedef struct fixed_ddr_parm{ 463 int min_freq; 464 int max_freq; 465 fsl_ddr_cfg_regs_t *ddr_settings; 466 } fixed_ddr_parm_t; 467 #endif 468