1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef FSL_DDR_MAIN_H 10 #define FSL_DDR_MAIN_H 11 12 #include <fsl_ddrc_version.h> 13 #include <fsl_ddr_sdram.h> 14 #include <fsl_ddr_dimm_params.h> 15 16 #include <common_timing_params.h> 17 18 #ifdef CONFIG_SYS_FSL_DDR_LE 19 #define ddr_in32(a) in_le32(a) 20 #define ddr_out32(a, v) out_le32(a, v) 21 #else 22 #define ddr_in32(a) in_be32(a) 23 #define ddr_out32(a, v) out_be32(a, v) 24 #endif 25 26 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR 27 28 u32 fsl_ddr_get_version(void); 29 30 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 31 /* 32 * Bind the main DDR setup driver's generic names 33 * to this specific DDR technology. 34 */ 35 static __inline__ int 36 compute_dimm_parameters(const generic_spd_eeprom_t *spd, 37 dimm_params_t *pdimm, 38 unsigned int dimm_number) 39 { 40 return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); 41 } 42 #endif 43 44 /* 45 * Data Structures 46 * 47 * All data structures have to be on the stack 48 */ 49 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS 50 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR 51 52 typedef struct { 53 generic_spd_eeprom_t 54 spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 55 struct dimm_params_s 56 dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 57 memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; 58 common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; 59 fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; 60 } fsl_ddr_info_t; 61 62 /* Compute steps */ 63 #define STEP_GET_SPD (1 << 0) 64 #define STEP_COMPUTE_DIMM_PARMS (1 << 1) 65 #define STEP_COMPUTE_COMMON_PARMS (1 << 2) 66 #define STEP_GATHER_OPTS (1 << 3) 67 #define STEP_ASSIGN_ADDRESSES (1 << 4) 68 #define STEP_COMPUTE_REGS (1 << 5) 69 #define STEP_PROGRAM_REGS (1 << 6) 70 #define STEP_ALL 0xFFF 71 72 unsigned long long 73 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 74 unsigned int size_only); 75 76 const char *step_to_string(unsigned int step); 77 78 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, 79 fsl_ddr_cfg_regs_t *ddr, 80 const common_timing_params_t *common_dimm, 81 const dimm_params_t *dimm_parameters, 82 unsigned int dbw_capacity_adjust, 83 unsigned int size_only); 84 unsigned int compute_lowest_common_dimm_parameters( 85 const dimm_params_t *dimm_params, 86 common_timing_params_t *outpdimm, 87 unsigned int number_of_dimms); 88 unsigned int populate_memctl_options(int all_dimms_registered, 89 memctl_options_t *popts, 90 dimm_params_t *pdimm, 91 unsigned int ctrl_num); 92 void check_interleaving_options(fsl_ddr_info_t *pinfo); 93 94 unsigned int mclk_to_picos(unsigned int mclk); 95 unsigned int get_memory_clk_period_ps(void); 96 unsigned int picos_to_mclk(unsigned int picos); 97 void fsl_ddr_set_lawbar( 98 const common_timing_params_t *memctl_common_params, 99 unsigned int memctl_interleaved, 100 unsigned int ctrl_num); 101 102 int fsl_ddr_interactive_env_var_exists(void); 103 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); 104 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 105 unsigned int ctrl_num); 106 107 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 108 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); 109 void board_add_ram_info(int use_default); 110 111 /* processor specific function */ 112 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 113 unsigned int ctrl_num, int step); 114 115 /* board specific function */ 116 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 117 unsigned int controller_number, 118 unsigned int dimm_number); 119 #endif 120