1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef FSL_DDR_MAIN_H 10 #define FSL_DDR_MAIN_H 11 12 #include <fsl_ddr_sdram.h> 13 #include <fsl_ddr_dimm_params.h> 14 15 #include <common_timing_params.h> 16 17 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 18 /* 19 * Bind the main DDR setup driver's generic names 20 * to this specific DDR technology. 21 */ 22 static __inline__ int 23 compute_dimm_parameters(const generic_spd_eeprom_t *spd, 24 dimm_params_t *pdimm, 25 unsigned int dimm_number) 26 { 27 return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); 28 } 29 #endif 30 31 /* 32 * Data Structures 33 * 34 * All data structures have to be on the stack 35 */ 36 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS 37 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR 38 39 typedef struct { 40 generic_spd_eeprom_t 41 spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 42 struct dimm_params_s 43 dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 44 memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; 45 common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; 46 fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; 47 } fsl_ddr_info_t; 48 49 /* Compute steps */ 50 #define STEP_GET_SPD (1 << 0) 51 #define STEP_COMPUTE_DIMM_PARMS (1 << 1) 52 #define STEP_COMPUTE_COMMON_PARMS (1 << 2) 53 #define STEP_GATHER_OPTS (1 << 3) 54 #define STEP_ASSIGN_ADDRESSES (1 << 4) 55 #define STEP_COMPUTE_REGS (1 << 5) 56 #define STEP_PROGRAM_REGS (1 << 6) 57 #define STEP_ALL 0xFFF 58 59 unsigned long long 60 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 61 unsigned int size_only); 62 63 const char *step_to_string(unsigned int step); 64 65 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, 66 fsl_ddr_cfg_regs_t *ddr, 67 const common_timing_params_t *common_dimm, 68 const dimm_params_t *dimm_parameters, 69 unsigned int dbw_capacity_adjust, 70 unsigned int size_only); 71 unsigned int compute_lowest_common_dimm_parameters( 72 const dimm_params_t *dimm_params, 73 common_timing_params_t *outpdimm, 74 unsigned int number_of_dimms); 75 unsigned int populate_memctl_options(int all_dimms_registered, 76 memctl_options_t *popts, 77 dimm_params_t *pdimm, 78 unsigned int ctrl_num); 79 void check_interleaving_options(fsl_ddr_info_t *pinfo); 80 81 unsigned int mclk_to_picos(unsigned int mclk); 82 unsigned int get_memory_clk_period_ps(void); 83 unsigned int picos_to_mclk(unsigned int picos); 84 void fsl_ddr_set_lawbar( 85 const common_timing_params_t *memctl_common_params, 86 unsigned int memctl_interleaved, 87 unsigned int ctrl_num); 88 89 int fsl_ddr_interactive_env_var_exists(void); 90 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); 91 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 92 unsigned int ctrl_num); 93 94 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 95 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); 96 97 /* processor specific function */ 98 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 99 unsigned int ctrl_num, int step); 100 101 /* board specific function */ 102 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 103 unsigned int controller_number, 104 unsigned int dimm_number); 105 #endif 106