1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 25614e71bSYork Sun /* 334e026f9SYork Sun * Copyright 2008-2014 Freescale Semiconductor, Inc. 45614e71bSYork Sun */ 55614e71bSYork Sun 65614e71bSYork Sun #ifndef FSL_DDR_MAIN_H 75614e71bSYork Sun #define FSL_DDR_MAIN_H 85614e71bSYork Sun 934e026f9SYork Sun #include <fsl_ddrc_version.h> 105614e71bSYork Sun #include <fsl_ddr_sdram.h> 115614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 125614e71bSYork Sun 135614e71bSYork Sun #include <common_timing_params.h> 145614e71bSYork Sun 151d71efbbSYork Sun #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 161d71efbbSYork Sun /* All controllers are for main memory */ 1751370d56SYork Sun #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS 181d71efbbSYork Sun #endif 191d71efbbSYork Sun 204e5b1bd0SYork Sun #ifdef CONFIG_SYS_FSL_DDR_LE 214e5b1bd0SYork Sun #define ddr_in32(a) in_le32(a) 224e5b1bd0SYork Sun #define ddr_out32(a, v) out_le32(a, v) 23dda3b610SYork Sun #define ddr_setbits32(a, v) setbits_le32(a, v) 24dda3b610SYork Sun #define ddr_clrbits32(a, v) clrbits_le32(a, v) 25dda3b610SYork Sun #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) 264e5b1bd0SYork Sun #else 274e5b1bd0SYork Sun #define ddr_in32(a) in_be32(a) 284e5b1bd0SYork Sun #define ddr_out32(a, v) out_be32(a, v) 29dda3b610SYork Sun #define ddr_setbits32(a, v) setbits_be32(a, v) 30dda3b610SYork Sun #define ddr_clrbits32(a, v) clrbits_be32(a, v) 31dda3b610SYork Sun #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) 324e5b1bd0SYork Sun #endif 334e5b1bd0SYork Sun 3466869f95SYork Sun u32 fsl_ddr_get_version(unsigned int ctrl_num); 3534e026f9SYork Sun 365614e71bSYork Sun #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 375614e71bSYork Sun /* 385614e71bSYork Sun * Bind the main DDR setup driver's generic names 395614e71bSYork Sun * to this specific DDR technology. 405614e71bSYork Sun */ 415614e71bSYork Sun static __inline__ int 4203e664d8SYork Sun compute_dimm_parameters(const unsigned int ctrl_num, 4303e664d8SYork Sun const generic_spd_eeprom_t *spd, 445614e71bSYork Sun dimm_params_t *pdimm, 455614e71bSYork Sun unsigned int dimm_number) 465614e71bSYork Sun { 4703e664d8SYork Sun return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); 485614e71bSYork Sun } 495614e71bSYork Sun #endif 505614e71bSYork Sun 515614e71bSYork Sun /* 525614e71bSYork Sun * Data Structures 535614e71bSYork Sun * 545614e71bSYork Sun * All data structures have to be on the stack 555614e71bSYork Sun */ 565614e71bSYork Sun #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR 575614e71bSYork Sun 585614e71bSYork Sun typedef struct { 595614e71bSYork Sun generic_spd_eeprom_t 605614e71bSYork Sun spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 615614e71bSYork Sun struct dimm_params_s 625614e71bSYork Sun dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 635614e71bSYork Sun memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; 645614e71bSYork Sun common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; 655614e71bSYork Sun fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; 661d71efbbSYork Sun unsigned int first_ctrl; 671d71efbbSYork Sun unsigned int num_ctrls; 681d71efbbSYork Sun unsigned long long mem_base; 691d71efbbSYork Sun unsigned int dimm_slots_per_ctrl; 701d71efbbSYork Sun int (*board_need_mem_reset)(void); 711d71efbbSYork Sun void (*board_mem_reset)(void); 721d71efbbSYork Sun void (*board_mem_de_reset)(void); 735614e71bSYork Sun } fsl_ddr_info_t; 745614e71bSYork Sun 755614e71bSYork Sun /* Compute steps */ 765614e71bSYork Sun #define STEP_GET_SPD (1 << 0) 775614e71bSYork Sun #define STEP_COMPUTE_DIMM_PARMS (1 << 1) 785614e71bSYork Sun #define STEP_COMPUTE_COMMON_PARMS (1 << 2) 795614e71bSYork Sun #define STEP_GATHER_OPTS (1 << 3) 805614e71bSYork Sun #define STEP_ASSIGN_ADDRESSES (1 << 4) 815614e71bSYork Sun #define STEP_COMPUTE_REGS (1 << 5) 825614e71bSYork Sun #define STEP_PROGRAM_REGS (1 << 6) 835614e71bSYork Sun #define STEP_ALL 0xFFF 845614e71bSYork Sun 855614e71bSYork Sun unsigned long long 865614e71bSYork Sun fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 875614e71bSYork Sun unsigned int size_only); 885614e71bSYork Sun const char *step_to_string(unsigned int step); 895614e71bSYork Sun 9003e664d8SYork Sun unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, 9103e664d8SYork Sun const memctl_options_t *popts, 925614e71bSYork Sun fsl_ddr_cfg_regs_t *ddr, 935614e71bSYork Sun const common_timing_params_t *common_dimm, 945614e71bSYork Sun const dimm_params_t *dimm_parameters, 955614e71bSYork Sun unsigned int dbw_capacity_adjust, 965614e71bSYork Sun unsigned int size_only); 975614e71bSYork Sun unsigned int compute_lowest_common_dimm_parameters( 9803e664d8SYork Sun const unsigned int ctrl_num, 995614e71bSYork Sun const dimm_params_t *dimm_params, 1005614e71bSYork Sun common_timing_params_t *outpdimm, 1015614e71bSYork Sun unsigned int number_of_dimms); 10256848428SYork Sun unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, 1035614e71bSYork Sun memctl_options_t *popts, 1045614e71bSYork Sun dimm_params_t *pdimm, 1055614e71bSYork Sun unsigned int ctrl_num); 1065614e71bSYork Sun void check_interleaving_options(fsl_ddr_info_t *pinfo); 1075614e71bSYork Sun 10803e664d8SYork Sun unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); 10903e664d8SYork Sun unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); 11003e664d8SYork Sun unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); 1115614e71bSYork Sun void fsl_ddr_set_lawbar( 1125614e71bSYork Sun const common_timing_params_t *memctl_common_params, 1135614e71bSYork Sun unsigned int memctl_interleaved, 1145614e71bSYork Sun unsigned int ctrl_num); 115e32d59a2SYork Sun void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, 116e32d59a2SYork Sun unsigned int last_ctrl); 1175614e71bSYork Sun 1185614e71bSYork Sun int fsl_ddr_interactive_env_var_exists(void); 1195614e71bSYork Sun unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); 1205614e71bSYork Sun void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 1211d71efbbSYork Sun unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); 1225614e71bSYork Sun 1235614e71bSYork Sun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 1245614e71bSYork Sun unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); 1254e5b1bd0SYork Sun void board_add_ram_info(int use_default); 1265614e71bSYork Sun 1275614e71bSYork Sun /* processor specific function */ 1285614e71bSYork Sun void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 1295614e71bSYork Sun unsigned int ctrl_num, int step); 13061bd2f75SYork Sun void remove_unused_controllers(fsl_ddr_info_t *info); 1315614e71bSYork Sun 1325614e71bSYork Sun /* board specific function */ 1335614e71bSYork Sun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 1345614e71bSYork Sun unsigned int controller_number, 1355614e71bSYork Sun unsigned int dimm_number); 136b92557cdSYork Sun void update_spd_address(unsigned int ctrl_num, 137b92557cdSYork Sun unsigned int slot, 138b92557cdSYork Sun unsigned int *addr); 13902fb2761SShengzhou Liu 14002fb2761SShengzhou Liu void erratum_a009942_check_cpo(void); 1415614e71bSYork Sun #endif 142