15614e71bSYork Sun /* 234e026f9SYork Sun * Copyright 2008-2014 Freescale Semiconductor, Inc. 35614e71bSYork Sun * 45614e71bSYork Sun * This program is free software; you can redistribute it and/or 55614e71bSYork Sun * modify it under the terms of the GNU General Public License 65614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 75614e71bSYork Sun */ 85614e71bSYork Sun 95614e71bSYork Sun #ifndef FSL_DDR_MAIN_H 105614e71bSYork Sun #define FSL_DDR_MAIN_H 115614e71bSYork Sun 1234e026f9SYork Sun #include <fsl_ddrc_version.h> 135614e71bSYork Sun #include <fsl_ddr_sdram.h> 145614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 155614e71bSYork Sun 165614e71bSYork Sun #include <common_timing_params.h> 175614e71bSYork Sun 181d71efbbSYork Sun #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 191d71efbbSYork Sun /* All controllers are for main memory */ 201d71efbbSYork Sun #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS 211d71efbbSYork Sun #endif 221d71efbbSYork Sun 234e5b1bd0SYork Sun #ifdef CONFIG_SYS_FSL_DDR_LE 244e5b1bd0SYork Sun #define ddr_in32(a) in_le32(a) 254e5b1bd0SYork Sun #define ddr_out32(a, v) out_le32(a, v) 26dda3b610SYork Sun #define ddr_setbits32(a, v) setbits_le32(a, v) 27dda3b610SYork Sun #define ddr_clrbits32(a, v) clrbits_le32(a, v) 28dda3b610SYork Sun #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) 294e5b1bd0SYork Sun #else 304e5b1bd0SYork Sun #define ddr_in32(a) in_be32(a) 314e5b1bd0SYork Sun #define ddr_out32(a, v) out_be32(a, v) 32dda3b610SYork Sun #define ddr_setbits32(a, v) setbits_be32(a, v) 33dda3b610SYork Sun #define ddr_clrbits32(a, v) clrbits_be32(a, v) 34dda3b610SYork Sun #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) 354e5b1bd0SYork Sun #endif 364e5b1bd0SYork Sun 3766869f95SYork Sun u32 fsl_ddr_get_version(unsigned int ctrl_num); 3834e026f9SYork Sun 395614e71bSYork Sun #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 405614e71bSYork Sun /* 415614e71bSYork Sun * Bind the main DDR setup driver's generic names 425614e71bSYork Sun * to this specific DDR technology. 435614e71bSYork Sun */ 445614e71bSYork Sun static __inline__ int 4503e664d8SYork Sun compute_dimm_parameters(const unsigned int ctrl_num, 4603e664d8SYork Sun const generic_spd_eeprom_t *spd, 475614e71bSYork Sun dimm_params_t *pdimm, 485614e71bSYork Sun unsigned int dimm_number) 495614e71bSYork Sun { 5003e664d8SYork Sun return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); 515614e71bSYork Sun } 525614e71bSYork Sun #endif 535614e71bSYork Sun 545614e71bSYork Sun /* 555614e71bSYork Sun * Data Structures 565614e71bSYork Sun * 575614e71bSYork Sun * All data structures have to be on the stack 585614e71bSYork Sun */ 595614e71bSYork Sun #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS 605614e71bSYork Sun #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR 615614e71bSYork Sun 625614e71bSYork Sun typedef struct { 635614e71bSYork Sun generic_spd_eeprom_t 645614e71bSYork Sun spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 655614e71bSYork Sun struct dimm_params_s 665614e71bSYork Sun dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 675614e71bSYork Sun memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; 685614e71bSYork Sun common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; 695614e71bSYork Sun fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; 701d71efbbSYork Sun unsigned int first_ctrl; 711d71efbbSYork Sun unsigned int num_ctrls; 721d71efbbSYork Sun unsigned long long mem_base; 731d71efbbSYork Sun unsigned int dimm_slots_per_ctrl; 741d71efbbSYork Sun int (*board_need_mem_reset)(void); 751d71efbbSYork Sun void (*board_mem_reset)(void); 761d71efbbSYork Sun void (*board_mem_de_reset)(void); 775614e71bSYork Sun } fsl_ddr_info_t; 785614e71bSYork Sun 795614e71bSYork Sun /* Compute steps */ 805614e71bSYork Sun #define STEP_GET_SPD (1 << 0) 815614e71bSYork Sun #define STEP_COMPUTE_DIMM_PARMS (1 << 1) 825614e71bSYork Sun #define STEP_COMPUTE_COMMON_PARMS (1 << 2) 835614e71bSYork Sun #define STEP_GATHER_OPTS (1 << 3) 845614e71bSYork Sun #define STEP_ASSIGN_ADDRESSES (1 << 4) 855614e71bSYork Sun #define STEP_COMPUTE_REGS (1 << 5) 865614e71bSYork Sun #define STEP_PROGRAM_REGS (1 << 6) 875614e71bSYork Sun #define STEP_ALL 0xFFF 885614e71bSYork Sun 895614e71bSYork Sun unsigned long long 905614e71bSYork Sun fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 915614e71bSYork Sun unsigned int size_only); 925614e71bSYork Sun const char *step_to_string(unsigned int step); 935614e71bSYork Sun 9403e664d8SYork Sun unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, 9503e664d8SYork Sun const memctl_options_t *popts, 965614e71bSYork Sun fsl_ddr_cfg_regs_t *ddr, 975614e71bSYork Sun const common_timing_params_t *common_dimm, 985614e71bSYork Sun const dimm_params_t *dimm_parameters, 995614e71bSYork Sun unsigned int dbw_capacity_adjust, 1005614e71bSYork Sun unsigned int size_only); 1015614e71bSYork Sun unsigned int compute_lowest_common_dimm_parameters( 10203e664d8SYork Sun const unsigned int ctrl_num, 1035614e71bSYork Sun const dimm_params_t *dimm_params, 1045614e71bSYork Sun common_timing_params_t *outpdimm, 1055614e71bSYork Sun unsigned int number_of_dimms); 106*56848428SYork Sun unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, 1075614e71bSYork Sun memctl_options_t *popts, 1085614e71bSYork Sun dimm_params_t *pdimm, 1095614e71bSYork Sun unsigned int ctrl_num); 1105614e71bSYork Sun void check_interleaving_options(fsl_ddr_info_t *pinfo); 1115614e71bSYork Sun 11203e664d8SYork Sun unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); 11303e664d8SYork Sun unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); 11403e664d8SYork Sun unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); 1155614e71bSYork Sun void fsl_ddr_set_lawbar( 1165614e71bSYork Sun const common_timing_params_t *memctl_common_params, 1175614e71bSYork Sun unsigned int memctl_interleaved, 1185614e71bSYork Sun unsigned int ctrl_num); 119e32d59a2SYork Sun void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, 120e32d59a2SYork Sun unsigned int last_ctrl); 1215614e71bSYork Sun 1225614e71bSYork Sun int fsl_ddr_interactive_env_var_exists(void); 1235614e71bSYork Sun unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); 1245614e71bSYork Sun void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 1251d71efbbSYork Sun unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); 1265614e71bSYork Sun 1275614e71bSYork Sun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 1285614e71bSYork Sun unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); 1294e5b1bd0SYork Sun void board_add_ram_info(int use_default); 1305614e71bSYork Sun 1315614e71bSYork Sun /* processor specific function */ 1325614e71bSYork Sun void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 1335614e71bSYork Sun unsigned int ctrl_num, int step); 1345614e71bSYork Sun 1355614e71bSYork Sun /* board specific function */ 1365614e71bSYork Sun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 1375614e71bSYork Sun unsigned int controller_number, 1385614e71bSYork Sun unsigned int dimm_number); 139b92557cdSYork Sun void update_spd_address(unsigned int ctrl_num, 140b92557cdSYork Sun unsigned int slot, 141b92557cdSYork Sun unsigned int *addr); 1425614e71bSYork Sun #endif 143