1*5614e71bSYork Sun /* 2*5614e71bSYork Sun * Copyright 2008-2011 Freescale Semiconductor, Inc. 3*5614e71bSYork Sun * 4*5614e71bSYork Sun * This program is free software; you can redistribute it and/or 5*5614e71bSYork Sun * modify it under the terms of the GNU General Public License 6*5614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 7*5614e71bSYork Sun */ 8*5614e71bSYork Sun 9*5614e71bSYork Sun #ifndef FSL_DDR_MAIN_H 10*5614e71bSYork Sun #define FSL_DDR_MAIN_H 11*5614e71bSYork Sun 12*5614e71bSYork Sun #include <fsl_ddr_sdram.h> 13*5614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 14*5614e71bSYork Sun 15*5614e71bSYork Sun #include <common_timing_params.h> 16*5614e71bSYork Sun 17*5614e71bSYork Sun #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) 18*5614e71bSYork Sun /* 19*5614e71bSYork Sun * Bind the main DDR setup driver's generic names 20*5614e71bSYork Sun * to this specific DDR technology. 21*5614e71bSYork Sun */ 22*5614e71bSYork Sun static __inline__ int 23*5614e71bSYork Sun compute_dimm_parameters(const generic_spd_eeprom_t *spd, 24*5614e71bSYork Sun dimm_params_t *pdimm, 25*5614e71bSYork Sun unsigned int dimm_number) 26*5614e71bSYork Sun { 27*5614e71bSYork Sun return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); 28*5614e71bSYork Sun } 29*5614e71bSYork Sun #endif 30*5614e71bSYork Sun 31*5614e71bSYork Sun /* 32*5614e71bSYork Sun * Data Structures 33*5614e71bSYork Sun * 34*5614e71bSYork Sun * All data structures have to be on the stack 35*5614e71bSYork Sun */ 36*5614e71bSYork Sun #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS 37*5614e71bSYork Sun #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR 38*5614e71bSYork Sun 39*5614e71bSYork Sun typedef struct { 40*5614e71bSYork Sun generic_spd_eeprom_t 41*5614e71bSYork Sun spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 42*5614e71bSYork Sun struct dimm_params_s 43*5614e71bSYork Sun dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; 44*5614e71bSYork Sun memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; 45*5614e71bSYork Sun common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; 46*5614e71bSYork Sun fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; 47*5614e71bSYork Sun } fsl_ddr_info_t; 48*5614e71bSYork Sun 49*5614e71bSYork Sun /* Compute steps */ 50*5614e71bSYork Sun #define STEP_GET_SPD (1 << 0) 51*5614e71bSYork Sun #define STEP_COMPUTE_DIMM_PARMS (1 << 1) 52*5614e71bSYork Sun #define STEP_COMPUTE_COMMON_PARMS (1 << 2) 53*5614e71bSYork Sun #define STEP_GATHER_OPTS (1 << 3) 54*5614e71bSYork Sun #define STEP_ASSIGN_ADDRESSES (1 << 4) 55*5614e71bSYork Sun #define STEP_COMPUTE_REGS (1 << 5) 56*5614e71bSYork Sun #define STEP_PROGRAM_REGS (1 << 6) 57*5614e71bSYork Sun #define STEP_ALL 0xFFF 58*5614e71bSYork Sun 59*5614e71bSYork Sun unsigned long long 60*5614e71bSYork Sun fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, 61*5614e71bSYork Sun unsigned int size_only); 62*5614e71bSYork Sun 63*5614e71bSYork Sun const char *step_to_string(unsigned int step); 64*5614e71bSYork Sun 65*5614e71bSYork Sun unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, 66*5614e71bSYork Sun fsl_ddr_cfg_regs_t *ddr, 67*5614e71bSYork Sun const common_timing_params_t *common_dimm, 68*5614e71bSYork Sun const dimm_params_t *dimm_parameters, 69*5614e71bSYork Sun unsigned int dbw_capacity_adjust, 70*5614e71bSYork Sun unsigned int size_only); 71*5614e71bSYork Sun unsigned int compute_lowest_common_dimm_parameters( 72*5614e71bSYork Sun const dimm_params_t *dimm_params, 73*5614e71bSYork Sun common_timing_params_t *outpdimm, 74*5614e71bSYork Sun unsigned int number_of_dimms); 75*5614e71bSYork Sun unsigned int populate_memctl_options(int all_dimms_registered, 76*5614e71bSYork Sun memctl_options_t *popts, 77*5614e71bSYork Sun dimm_params_t *pdimm, 78*5614e71bSYork Sun unsigned int ctrl_num); 79*5614e71bSYork Sun void check_interleaving_options(fsl_ddr_info_t *pinfo); 80*5614e71bSYork Sun 81*5614e71bSYork Sun unsigned int mclk_to_picos(unsigned int mclk); 82*5614e71bSYork Sun unsigned int get_memory_clk_period_ps(void); 83*5614e71bSYork Sun unsigned int picos_to_mclk(unsigned int picos); 84*5614e71bSYork Sun void fsl_ddr_set_lawbar( 85*5614e71bSYork Sun const common_timing_params_t *memctl_common_params, 86*5614e71bSYork Sun unsigned int memctl_interleaved, 87*5614e71bSYork Sun unsigned int ctrl_num); 88*5614e71bSYork Sun 89*5614e71bSYork Sun int fsl_ddr_interactive_env_var_exists(void); 90*5614e71bSYork Sun unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); 91*5614e71bSYork Sun void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, 92*5614e71bSYork Sun unsigned int ctrl_num); 93*5614e71bSYork Sun 94*5614e71bSYork Sun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); 95*5614e71bSYork Sun unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); 96*5614e71bSYork Sun 97*5614e71bSYork Sun /* processor specific function */ 98*5614e71bSYork Sun void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 99*5614e71bSYork Sun unsigned int ctrl_num, int step); 100*5614e71bSYork Sun 101*5614e71bSYork Sun /* board specific function */ 102*5614e71bSYork Sun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 103*5614e71bSYork Sun unsigned int controller_number, 104*5614e71bSYork Sun unsigned int dimm_number); 105*5614e71bSYork Sun #endif 106