1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_MC_H__ 8 #define __FSL_MC_H__ 9 10 #include <common.h> 11 12 #define MC_CCSR_BASE_ADDR \ 13 ((struct mc_ccsr_registers __iomem *)0x8340000) 14 15 #define BIT(x) (1 << (x)) 16 #define GCR1_P1_STOP BIT(31) 17 #define GCR1_P2_STOP BIT(30) 18 #define GCR1_P1_DE_RST BIT(23) 19 #define GCR1_P2_DE_RST BIT(22) 20 #define GCR1_M1_DE_RST BIT(15) 21 #define GCR1_M2_DE_RST BIT(14) 22 #define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) 23 #define GSR_FS_MASK 0x3fffffff 24 25 #define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) 26 #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000) 27 #define SOC_MC_PORTAL_STRIDE 0x10000 28 29 #define SOC_MC_PORTAL_ADDR(_portal_id) \ 30 ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ 31 (_portal_id) * SOC_MC_PORTAL_STRIDE)) 32 33 struct mc_ccsr_registers { 34 u32 reg_gcr1; 35 u32 reserved1; 36 u32 reg_gsr; 37 u32 reserved2; 38 u32 reg_sicbalr; 39 u32 reg_sicbahr; 40 u32 reg_sicapr; 41 u32 reserved3; 42 u32 reg_mcfbalr; 43 u32 reg_mcfbahr; 44 u32 reg_mcfapr; 45 u32 reserved4[0x2f1]; 46 u32 reg_psr; 47 u32 reserved5; 48 u32 reg_brr[2]; 49 u32 reserved6[0x80]; 50 u32 reg_error[]; 51 }; 52 53 int get_mc_boot_status(void); 54 unsigned long mc_get_dram_block_size(void); 55 int fsl_mc_ldpaa_init(bd_t *bis); 56 void fsl_mc_ldpaa_exit(bd_t *bis); 57 #endif 58