xref: /openbmc/u-boot/include/fsl-mc/fsl_mc.h (revision 2eb48ff7)
1 /*
2  * Copyright (C) 2014 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __FSL_MC_H__
8 #define __FSL_MC_H__
9 
10 #include <common.h>
11 
12 #define MC_CCSR_BASE_ADDR \
13 	((struct mc_ccsr_registers __iomem *)0x8340000)
14 
15 #define GCR1_P1_STOP		BIT(31)
16 #define GCR1_P2_STOP		BIT(30)
17 #define GCR1_P1_DE_RST		BIT(23)
18 #define GCR1_P2_DE_RST		BIT(22)
19 #define GCR1_M1_DE_RST		BIT(15)
20 #define GCR1_M2_DE_RST		BIT(14)
21 #define GCR1_M_ALL_DE_RST	(GCR1_M1_DE_RST | GCR1_M2_DE_RST)
22 #define GSR_FS_MASK		0x3fffffff
23 
24 #define SOC_MC_PORTALS_BASE_ADDR    ((void __iomem *)0x00080C000000)
25 #define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
26 #define SOC_MC_PORTAL_STRIDE	    0x10000
27 
28 #define SOC_MC_PORTAL_ADDR(_portal_id) \
29 	((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
30 	 (_portal_id) * SOC_MC_PORTAL_STRIDE))
31 
32 #define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \
33 	((_portal_offset) / SOC_MC_PORTAL_STRIDE)
34 
35 struct mc_ccsr_registers {
36 	u32 reg_gcr1;
37 	u32 reserved1;
38 	u32 reg_gsr;
39 	u32 reserved2;
40 	u32 reg_sicbalr;
41 	u32 reg_sicbahr;
42 	u32 reg_sicapr;
43 	u32 reserved3;
44 	u32 reg_mcfbalr;
45 	u32 reg_mcfbahr;
46 	u32 reg_mcfapr;
47 	u32 reserved4[0x2f1];
48 	u32 reg_psr;
49 	u32 reserved5;
50 	u32 reg_brr[2];
51 	u32 reserved6[0x80];
52 	u32 reg_error[];
53 };
54 
55 int get_mc_boot_status(void);
56 int get_dpl_apply_status(void);
57 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
58 int get_aiop_apply_status(void);
59 #endif
60 u64 mc_get_dram_addr(void);
61 unsigned long mc_get_dram_block_size(void);
62 int fsl_mc_ldpaa_init(bd_t *bis);
63 int fsl_mc_ldpaa_exit(bd_t *bd);
64 void mc_env_boot(void);
65 #endif
66