1 /* 2 * (C) Copyright 2002 3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <linux/types.h> /* for ulong typedef */ 9 10 #ifndef _FPGA_H_ 11 #define _FPGA_H_ 12 13 #ifndef CONFIG_MAX_FPGA_DEVICES 14 #define CONFIG_MAX_FPGA_DEVICES 5 15 #endif 16 17 /* fpga_xxxx function return value definitions */ 18 #define FPGA_SUCCESS 0 19 #define FPGA_FAIL -1 20 21 /* device numbers must be non-negative */ 22 #define FPGA_INVALID_DEVICE -1 23 24 /* root data type defintions */ 25 typedef enum { /* typedef fpga_type */ 26 fpga_min_type, /* range check value */ 27 fpga_xilinx, /* Xilinx Family) */ 28 fpga_altera, /* unimplemented */ 29 fpga_lattice, /* Lattice family */ 30 fpga_undefined /* invalid range check value */ 31 } fpga_type; /* end, typedef fpga_type */ 32 33 typedef struct { /* typedef fpga_desc */ 34 fpga_type devtype; /* switch value to select sub-functions */ 35 void *devdesc; /* real device descriptor */ 36 } fpga_desc; /* end, typedef fpga_desc */ 37 38 typedef struct { /* typedef fpga_desc */ 39 unsigned int blocksize; 40 char *interface; 41 char *dev_part; 42 char *filename; 43 int fstype; 44 } fpga_fs_info; 45 46 typedef enum { 47 BIT_FULL = 0, 48 BIT_PARTIAL, 49 } bitstream_type; 50 51 /* root function definitions */ 52 void fpga_init(void); 53 int fpga_add(fpga_type devtype, void *desc); 54 int fpga_count(void); 55 const fpga_desc *const fpga_get_desc(int devnum); 56 int fpga_load(int devnum, const void *buf, size_t bsize, 57 bitstream_type bstype); 58 int fpga_fsload(int devnum, const void *buf, size_t size, 59 fpga_fs_info *fpga_fsinfo); 60 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 61 bitstream_type bstype); 62 int fpga_dump(int devnum, const void *buf, size_t bsize); 63 int fpga_info(int devnum); 64 const fpga_desc *const fpga_validate(int devnum, const void *buf, 65 size_t bsize, char *fn); 66 67 #endif /* _FPGA_H_ */ 68