1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2002 4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 5 */ 6 7 #include <linux/types.h> /* for ulong typedef */ 8 9 #ifndef _FPGA_H_ 10 #define _FPGA_H_ 11 12 #ifndef CONFIG_MAX_FPGA_DEVICES 13 #define CONFIG_MAX_FPGA_DEVICES 5 14 #endif 15 16 /* fpga_xxxx function return value definitions */ 17 #define FPGA_SUCCESS 0 18 #define FPGA_FAIL -1 19 20 /* device numbers must be non-negative */ 21 #define FPGA_INVALID_DEVICE -1 22 23 /* root data type defintions */ 24 typedef enum { /* typedef fpga_type */ 25 fpga_min_type, /* range check value */ 26 fpga_xilinx, /* Xilinx Family) */ 27 fpga_altera, /* unimplemented */ 28 fpga_lattice, /* Lattice family */ 29 fpga_undefined /* invalid range check value */ 30 } fpga_type; /* end, typedef fpga_type */ 31 32 typedef struct { /* typedef fpga_desc */ 33 fpga_type devtype; /* switch value to select sub-functions */ 34 void *devdesc; /* real device descriptor */ 35 } fpga_desc; /* end, typedef fpga_desc */ 36 37 typedef struct { /* typedef fpga_desc */ 38 unsigned int blocksize; 39 char *interface; 40 char *dev_part; 41 char *filename; 42 int fstype; 43 } fpga_fs_info; 44 45 typedef enum { 46 BIT_FULL = 0, 47 BIT_PARTIAL, 48 BIT_NONE = 0xFF, 49 } bitstream_type; 50 51 /* root function definitions */ 52 void fpga_init(void); 53 int fpga_add(fpga_type devtype, void *desc); 54 int fpga_count(void); 55 const fpga_desc *const fpga_get_desc(int devnum); 56 int fpga_is_partial_data(int devnum, size_t img_len); 57 int fpga_load(int devnum, const void *buf, size_t bsize, 58 bitstream_type bstype); 59 int fpga_fsload(int devnum, const void *buf, size_t size, 60 fpga_fs_info *fpga_fsinfo); 61 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 62 bitstream_type bstype); 63 int fpga_dump(int devnum, const void *buf, size_t bsize); 64 int fpga_info(int devnum); 65 const fpga_desc *const fpga_validate(int devnum, const void *buf, 66 size_t bsize, char *fn); 67 68 #endif /* _FPGA_H_ */ 69