183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2024a26bcSwdenk /* 3024a26bcSwdenk * (C) Copyright 2002 4024a26bcSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 5024a26bcSwdenk */ 6024a26bcSwdenk 7024a26bcSwdenk #include <linux/types.h> /* for ulong typedef */ 8024a26bcSwdenk 9024a26bcSwdenk #ifndef _FPGA_H_ 10024a26bcSwdenk #define _FPGA_H_ 11024a26bcSwdenk 12024a26bcSwdenk #ifndef CONFIG_MAX_FPGA_DEVICES 13024a26bcSwdenk #define CONFIG_MAX_FPGA_DEVICES 5 14024a26bcSwdenk #endif 15024a26bcSwdenk 16024a26bcSwdenk /* fpga_xxxx function return value definitions */ 17024a26bcSwdenk #define FPGA_SUCCESS 0 18024a26bcSwdenk #define FPGA_FAIL -1 19024a26bcSwdenk 20024a26bcSwdenk /* device numbers must be non-negative */ 21024a26bcSwdenk #define FPGA_INVALID_DEVICE -1 22024a26bcSwdenk 23*cedd48e2SSiva Durga Prasad Paladugu #define FPGA_ENC_USR_KEY 1 24*cedd48e2SSiva Durga Prasad Paladugu #define FPGA_NO_ENC_OR_NO_AUTH 2 25*cedd48e2SSiva Durga Prasad Paladugu 26024a26bcSwdenk /* root data type defintions */ 27024a26bcSwdenk typedef enum { /* typedef fpga_type */ 28024a26bcSwdenk fpga_min_type, /* range check value */ 29024a26bcSwdenk fpga_xilinx, /* Xilinx Family) */ 30024a26bcSwdenk fpga_altera, /* unimplemented */ 313b8ac464SStefano Babic fpga_lattice, /* Lattice family */ 32024a26bcSwdenk fpga_undefined /* invalid range check value */ 33024a26bcSwdenk } fpga_type; /* end, typedef fpga_type */ 34024a26bcSwdenk 35024a26bcSwdenk typedef struct { /* typedef fpga_desc */ 36024a26bcSwdenk fpga_type devtype; /* switch value to select sub-functions */ 37024a26bcSwdenk void *devdesc; /* real device descriptor */ 38024a26bcSwdenk } fpga_desc; /* end, typedef fpga_desc */ 39024a26bcSwdenk 401a897668SSiva Durga Prasad Paladugu typedef struct { /* typedef fpga_desc */ 411a897668SSiva Durga Prasad Paladugu unsigned int blocksize; 421a897668SSiva Durga Prasad Paladugu char *interface; 431a897668SSiva Durga Prasad Paladugu char *dev_part; 441a897668SSiva Durga Prasad Paladugu char *filename; 451a897668SSiva Durga Prasad Paladugu int fstype; 461a897668SSiva Durga Prasad Paladugu } fpga_fs_info; 47024a26bcSwdenk 48*cedd48e2SSiva Durga Prasad Paladugu struct fpga_secure_info { 49*cedd48e2SSiva Durga Prasad Paladugu u8 *userkey_addr; 50*cedd48e2SSiva Durga Prasad Paladugu u8 authflag; 51*cedd48e2SSiva Durga Prasad Paladugu u8 encflag; 52*cedd48e2SSiva Durga Prasad Paladugu }; 53*cedd48e2SSiva Durga Prasad Paladugu 547a78bd26SMichal Simek typedef enum { 557a78bd26SMichal Simek BIT_FULL = 0, 5667193864SMichal Simek BIT_PARTIAL, 57ddbcf8f2SSiva Durga Prasad Paladugu BIT_NONE = 0xFF, 587a78bd26SMichal Simek } bitstream_type; 597a78bd26SMichal Simek 60024a26bcSwdenk /* root function definitions */ 616583505cSMichal Simek void fpga_init(void); 626583505cSMichal Simek int fpga_add(fpga_type devtype, void *desc); 636583505cSMichal Simek int fpga_count(void); 64ebd322deSMichal Simek const fpga_desc *const fpga_get_desc(int devnum); 658b93a92fSGoldschmidt Simon int fpga_is_partial_data(int devnum, size_t img_len); 666583505cSMichal Simek int fpga_load(int devnum, const void *buf, size_t bsize, 677a78bd26SMichal Simek bitstream_type bstype); 686583505cSMichal Simek int fpga_fsload(int devnum, const void *buf, size_t size, 691a897668SSiva Durga Prasad Paladugu fpga_fs_info *fpga_fsinfo); 70*cedd48e2SSiva Durga Prasad Paladugu int fpga_loads(int devnum, const void *buf, size_t size, 71*cedd48e2SSiva Durga Prasad Paladugu struct fpga_secure_info *fpga_sec_info); 726583505cSMichal Simek int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 737a78bd26SMichal Simek bitstream_type bstype); 746583505cSMichal Simek int fpga_dump(int devnum, const void *buf, size_t bsize); 756583505cSMichal Simek int fpga_info(int devnum); 766583505cSMichal Simek const fpga_desc *const fpga_validate(int devnum, const void *buf, 776631db47SMichal Simek size_t bsize, char *fn); 78024a26bcSwdenk 79024a26bcSwdenk #endif /* _FPGA_H_ */ 80