1 /* 2 * Watchdog driver for the FTWDT010 Watch Dog Driver 3 * 4 * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) 5 * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu> 6 * Based on SoftDog driver by Alan Cox <alan@redhat.com> 7 * 8 * Copyright (C) 2011 Andes Technology Corporation 9 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 * 13 * 27/11/2004 Initial release, Faraday. 14 * 12/01/2011 Port to u-boot, Macpaul Lin. 15 */ 16 17 #ifndef __FTWDT010_H 18 #define __FTWDT010_H 19 20 struct ftwdt010_wdt { 21 unsigned int wdcounter; /* Counter Reg - 0x00 */ 22 unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ 23 unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ 24 unsigned int wdcr; /* Control Reg - 0x0c */ 25 unsigned int wdstatus; /* Status Reg - 0x10 */ 26 unsigned int wdclear; /* Timer Clear - 0x14 */ 27 unsigned int wdintrlen; /* Interrupt Length - 0x18 */ 28 }; 29 30 /* 31 * WDLOAD - Counter Auto Reload Register 32 * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. 33 * Which means in a 66MHz system, the period of Watch Dog timer reset is 34 * one second. 35 */ 36 #define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) 37 38 /* 39 * WDRESTART - Watch Dog Timer Counter Restart Register 40 * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will 41 * automatically reload WDLOAD to WDCOUNTER and restart counting. 42 */ 43 #define FTWDT010_WDRESTART_MAGIC 0x5AB9 44 45 /* WDCR - Watch Dog Timer Control Register */ 46 #define FTWDT010_WDCR_ENABLE (1 << 0) 47 #define FTWDT010_WDCR_RST (1 << 1) 48 #define FTWDT010_WDCR_INTR (1 << 2) 49 /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ 50 #define FTWDT010_WDCR_EXT (1 << 3) 51 /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. 52 * The clock source PCLK cannot be gated when system sleeps, even if 53 * WDCLOCK bit is turned on. 54 * 55 * Faraday's Watch Dog timer can be driven by an external clock. The 56 * programmer just needs to write one to WdCR[WdClock] bit. 57 * 58 * Note: There is a limitation between EXTCLK and PCLK: 59 * EXTCLK cycle time / PCLK cycle time > 2. 60 * If the system does not need an external clock, 61 * just keep WdCR[WdClock] bit in its default value. 62 */ 63 #define FTWDT010_WDCR_CLOCK (1 << 4) 64 65 /* 66 * WDSTATUS - Watch Dog Timer Status Register 67 * This bit is set when the counter reaches Zero 68 */ 69 #define FTWDT010_WDSTATUS(x) ((x) & 0x1) 70 71 /* 72 * WDCLEAR - Watch Dog Timer Clear Register 73 * Writing one to this register will clear WDSTATUS. 74 */ 75 #define FTWDT010_WDCLEAR (1 << 0) 76 77 /* 78 * WDINTRLEN - Watch Dog Timer Interrupt Length 79 * This register controls the duration length of wd_rst, wd_intr and wd_ext. 80 * The default value is 0xFF. 81 */ 82 #define FTWDT010_WDINTRLEN(x) ((x) & 0xff) 83 84 /* 85 * Variable timeout should be set in ms. 86 * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. 87 * WDLOAD = timeout * TIMEOUT_FACTOR. 88 */ 89 #define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ 90 91 void ftwdt010_wdt_reset(void); 92 void ftwdt010_wdt_disable(void); 93 94 #endif /* __FTWDT010_H */ 95