1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 20f7ffd75SMacpaul Lin /* 30f7ffd75SMacpaul Lin * (C) Copyright 2009 Faraday Technology 40f7ffd75SMacpaul Lin * Po-Yu Chuang <ratbert@faraday-tech.com> 50f7ffd75SMacpaul Lin */ 60f7ffd75SMacpaul Lin 70f7ffd75SMacpaul Lin /* 80f7ffd75SMacpaul Lin * Timer 90f7ffd75SMacpaul Lin */ 100f7ffd75SMacpaul Lin #ifndef __FTTMR010_H 110f7ffd75SMacpaul Lin #define __FTTMR010_H 120f7ffd75SMacpaul Lin 130f7ffd75SMacpaul Lin struct fttmr010 { 140f7ffd75SMacpaul Lin unsigned int timer1_counter; /* 0x00 */ 150f7ffd75SMacpaul Lin unsigned int timer1_load; /* 0x04 */ 160f7ffd75SMacpaul Lin unsigned int timer1_match1; /* 0x08 */ 170f7ffd75SMacpaul Lin unsigned int timer1_match2; /* 0x0c */ 180f7ffd75SMacpaul Lin unsigned int timer2_counter; /* 0x10 */ 190f7ffd75SMacpaul Lin unsigned int timer2_load; /* 0x14 */ 200f7ffd75SMacpaul Lin unsigned int timer2_match1; /* 0x18 */ 210f7ffd75SMacpaul Lin unsigned int timer2_match2; /* 0x1c */ 220f7ffd75SMacpaul Lin unsigned int timer3_counter; /* 0x20 */ 230f7ffd75SMacpaul Lin unsigned int timer3_load; /* 0x24 */ 240f7ffd75SMacpaul Lin unsigned int timer3_match1; /* 0x28 */ 250f7ffd75SMacpaul Lin unsigned int timer3_match2; /* 0x2c */ 260f7ffd75SMacpaul Lin unsigned int cr; /* 0x30 */ 270f7ffd75SMacpaul Lin unsigned int interrupt_state; /* 0x34 */ 280f7ffd75SMacpaul Lin unsigned int interrupt_mask; /* 0x38 */ 290f7ffd75SMacpaul Lin }; 300f7ffd75SMacpaul Lin 310f7ffd75SMacpaul Lin /* 320f7ffd75SMacpaul Lin * Timer Control Register 330f7ffd75SMacpaul Lin */ 340f7ffd75SMacpaul Lin #define FTTMR010_TM3_UPDOWN (1 << 11) 350f7ffd75SMacpaul Lin #define FTTMR010_TM2_UPDOWN (1 << 10) 360f7ffd75SMacpaul Lin #define FTTMR010_TM1_UPDOWN (1 << 9) 370f7ffd75SMacpaul Lin #define FTTMR010_TM3_OFENABLE (1 << 8) 380f7ffd75SMacpaul Lin #define FTTMR010_TM3_CLOCK (1 << 7) 390f7ffd75SMacpaul Lin #define FTTMR010_TM3_ENABLE (1 << 6) 400f7ffd75SMacpaul Lin #define FTTMR010_TM2_OFENABLE (1 << 5) 410f7ffd75SMacpaul Lin #define FTTMR010_TM2_CLOCK (1 << 4) 420f7ffd75SMacpaul Lin #define FTTMR010_TM2_ENABLE (1 << 3) 430f7ffd75SMacpaul Lin #define FTTMR010_TM1_OFENABLE (1 << 2) 440f7ffd75SMacpaul Lin #define FTTMR010_TM1_CLOCK (1 << 1) 450f7ffd75SMacpaul Lin #define FTTMR010_TM1_ENABLE (1 << 0) 460f7ffd75SMacpaul Lin 470f7ffd75SMacpaul Lin /* 480f7ffd75SMacpaul Lin * Timer Interrupt State & Mask Registers 490f7ffd75SMacpaul Lin */ 500f7ffd75SMacpaul Lin #define FTTMR010_TM3_OVERFLOW (1 << 8) 510f7ffd75SMacpaul Lin #define FTTMR010_TM3_MATCH2 (1 << 7) 520f7ffd75SMacpaul Lin #define FTTMR010_TM3_MATCH1 (1 << 6) 530f7ffd75SMacpaul Lin #define FTTMR010_TM2_OVERFLOW (1 << 5) 540f7ffd75SMacpaul Lin #define FTTMR010_TM2_MATCH2 (1 << 4) 550f7ffd75SMacpaul Lin #define FTTMR010_TM2_MATCH1 (1 << 3) 560f7ffd75SMacpaul Lin #define FTTMR010_TM1_OVERFLOW (1 << 2) 570f7ffd75SMacpaul Lin #define FTTMR010_TM1_MATCH2 (1 << 1) 580f7ffd75SMacpaul Lin #define FTTMR010_TM1_MATCH1 (1 << 0) 590f7ffd75SMacpaul Lin 600f7ffd75SMacpaul Lin #endif /* __FTTMR010_H */ 61