1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 25656b40bSMacpaul Lin /* 35656b40bSMacpaul Lin * (C) Copyright 2009 Faraday Technology 45656b40bSMacpaul Lin * Po-Yu Chuang <ratbert@faraday-tech.com> 55656b40bSMacpaul Lin */ 65656b40bSMacpaul Lin 75656b40bSMacpaul Lin /* 85656b40bSMacpaul Lin * SDRAM Controller 95656b40bSMacpaul Lin */ 105656b40bSMacpaul Lin #ifndef __FTSDMC020_H 115656b40bSMacpaul Lin #define __FTSDMC020_H 125656b40bSMacpaul Lin 135656b40bSMacpaul Lin #define FTSDMC020_OFFSET_TP0 0x00 145656b40bSMacpaul Lin #define FTSDMC020_OFFSET_TP1 0x04 155656b40bSMacpaul Lin #define FTSDMC020_OFFSET_CR 0x08 165656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK0_BSR 0x0C 175656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK1_BSR 0x10 185656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK2_BSR 0x14 195656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK3_BSR 0x18 205656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK4_BSR 0x1C 215656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK5_BSR 0x20 225656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK6_BSR 0x24 235656b40bSMacpaul Lin #define FTSDMC020_OFFSET_BANK7_BSR 0x28 245656b40bSMacpaul Lin #define FTSDMC020_OFFSET_ACR 0x34 255656b40bSMacpaul Lin 265656b40bSMacpaul Lin /* 275656b40bSMacpaul Lin * Timing Parametet 0 Register 285656b40bSMacpaul Lin */ 295656b40bSMacpaul Lin #define FTSDMC020_TP0_TCL(x) ((x) & 0x3) 305656b40bSMacpaul Lin #define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) 315656b40bSMacpaul Lin #define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) 325656b40bSMacpaul Lin #define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) 335656b40bSMacpaul Lin #define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) 345656b40bSMacpaul Lin #define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) 355656b40bSMacpaul Lin 365656b40bSMacpaul Lin /* 375656b40bSMacpaul Lin * Timing Parametet 1 Register 385656b40bSMacpaul Lin */ 395656b40bSMacpaul Lin #define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) 405656b40bSMacpaul Lin #define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) 415656b40bSMacpaul Lin #define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) 425656b40bSMacpaul Lin 435656b40bSMacpaul Lin /* 445656b40bSMacpaul Lin * Configuration Register 455656b40bSMacpaul Lin */ 465656b40bSMacpaul Lin #define FTSDMC020_CR_SREF (1 << 0) 475656b40bSMacpaul Lin #define FTSDMC020_CR_PWDN (1 << 1) 485656b40bSMacpaul Lin #define FTSDMC020_CR_ISMR (1 << 2) 495656b40bSMacpaul Lin #define FTSDMC020_CR_IREF (1 << 3) 505656b40bSMacpaul Lin #define FTSDMC020_CR_IPREC (1 << 4) 515656b40bSMacpaul Lin #define FTSDMC020_CR_REFTYPE (1 << 5) 525656b40bSMacpaul Lin 535656b40bSMacpaul Lin /* 545656b40bSMacpaul Lin * SDRAM External Bank Base/Size Register 555656b40bSMacpaul Lin */ 565656b40bSMacpaul Lin #define FTSDMC020_BANK_ENABLE (1 << 28) 575656b40bSMacpaul Lin 585656b40bSMacpaul Lin #define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) 595656b40bSMacpaul Lin 605656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X4 (0 << 12) 615656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X8 (1 << 12) 625656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X16 (2 << 12) 635656b40bSMacpaul Lin #define FTSDMC020_BANK_DDW_X32 (3 << 12) 645656b40bSMacpaul Lin 655656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_16M (0 << 8) 665656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_64M (1 << 8) 675656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_128M (2 << 8) 685656b40bSMacpaul Lin #define FTSDMC020_BANK_DSZ_256M (3 << 8) 695656b40bSMacpaul Lin 705656b40bSMacpaul Lin #define FTSDMC020_BANK_MBW_8 (0 << 4) 715656b40bSMacpaul Lin #define FTSDMC020_BANK_MBW_16 (1 << 4) 725656b40bSMacpaul Lin #define FTSDMC020_BANK_MBW_32 (2 << 4) 735656b40bSMacpaul Lin 745656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_1M 0x0 755656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_2M 0x1 765656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_4M 0x2 775656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_8M 0x3 785656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_16M 0x4 795656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_32M 0x5 805656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_64M 0x6 815656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_128M 0x7 825656b40bSMacpaul Lin #define FTSDMC020_BANK_SIZE_256M 0x8 835656b40bSMacpaul Lin 845656b40bSMacpaul Lin /* 855656b40bSMacpaul Lin * Arbiter Control Register 865656b40bSMacpaul Lin */ 875656b40bSMacpaul Lin #define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) 885656b40bSMacpaul Lin #define FTSDMC020_ACR_TOE (1 << 8) 895656b40bSMacpaul Lin 905656b40bSMacpaul Lin #endif /* __FTSDMC020_H */ 91