1 /* 2 * Faraday FTSDC010 Secure Digital Memory Card Host Controller 3 * 4 * Copyright (C) 2011 Andes Technology Corporation 5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #ifndef __FTSDC010_H 23 #define __FTSDC010_H 24 25 #ifndef __ASSEMBLY__ 26 27 /* sd controller register */ 28 struct ftsdc010_mmc { 29 unsigned int cmd; /* 0x00 - command reg */ 30 unsigned int argu; /* 0x04 - argument reg */ 31 unsigned int rsp0; /* 0x08 - response reg0 */ 32 unsigned int rsp1; /* 0x0c - response reg1 */ 33 unsigned int rsp2; /* 0x10 - response reg2 */ 34 unsigned int rsp3; /* 0x14 - response reg3 */ 35 unsigned int rsp_cmd; /* 0x18 - responded cmd reg */ 36 unsigned int dcr; /* 0x1c - data control reg */ 37 unsigned int dtr; /* 0x20 - data timer reg */ 38 unsigned int dlr; /* 0x24 - data length reg */ 39 unsigned int status; /* 0x28 - status reg */ 40 unsigned int clr; /* 0x2c - clear reg */ 41 unsigned int int_mask; /* 0x30 - intrrupt mask reg */ 42 unsigned int pcr; /* 0x34 - power control reg */ 43 unsigned int ccr; /* 0x38 - clock contorl reg */ 44 unsigned int bwr; /* 0x3c - bus width reg */ 45 unsigned int dwr; /* 0x40 - data window reg */ 46 #ifndef CONFIG_FTSDC010_SDIO 47 unsigned int feature; /* 0x44 - feature reg */ 48 unsigned int rev; /* 0x48 - revision reg */ 49 #else 50 unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */ 51 unsigned int gpo; /* 0x48 - gerenal purpose output */ 52 unsigned int reserved[8]; /* 0x50 - 0x68 reserved */ 53 unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */ 54 unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */ 55 unsigned int sdio_status; /* 0x74 - SDIO status regi */ 56 unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */ 57 unsigned int feature; /* 0x9c - feature reg */ 58 unsigned int rev; /* 0xa0 - revision reg */ 59 #endif /* CONFIG_FTSDC010_SDIO */ 60 }; 61 62 struct mmc_host { 63 struct ftsdc010_mmc *reg; 64 unsigned int version; /* SDHCI spec. version */ 65 unsigned int clock; /* Current clock (MHz) */ 66 unsigned int fifo_len; /* bytes */ 67 unsigned int last_opcode; /* Last OP Code */ 68 unsigned int card_type; /* Card type */ 69 }; 70 71 /* functions */ 72 int ftsdc010_mmc_init(int dev_index); 73 74 #endif /* __ASSEMBLY__ */ 75 76 /* global defines */ 77 #define FTSDC010_CMD_RETRY 0x100000 78 #define FTSDC010_PIO_RETRY 100 /* pio retry times */ 79 #define FTSDC010_DELAY_UNIT 100 /* 100 us */ 80 81 /* define from Linux kernel - include/linux/mmc/card.h */ 82 #define MMC_TYPE_SDIO 2 /* SDIO card */ 83 84 /* define for mmc layer */ 85 #define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) 86 87 /* this part is strange */ 88 #define FTSDC010_SDIO_CTRL1_REG 0x0000006C 89 #define FTSDC010_SDIO_CTRL2_REG 0x0000006C 90 #define FTSDC010_SDIO_STATUS_REG 0x00000070 91 92 /* 0x00 - command register */ 93 #define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0) 94 #define FTSDC010_CMD_NEED_RSP (1 << 6) 95 #define FTSDC010_CMD_LONG_RSP (1 << 7) 96 #define FTSDC010_CMD_APP_CMD (1 << 8) 97 #define FTSDC010_CMD_CMD_EN (1 << 9) 98 #define FTSDC010_CMD_SDC_RST (1 << 10) 99 #define FTSDC010_CMD_MMC_INT_STOP (1 << 11) 100 101 /* 0x18 - responded command register */ 102 #define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f) 103 #define FTSDC010_RSP_CMD_APP (1 << 6) 104 105 /* 0x1c - data control register */ 106 #define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0) 107 #define FTSDC010_DCR_DATA_WRITE (1 << 4) 108 #define FTSDC010_DCR_DMA_EN (1 << 5) 109 #define FTSDC010_DCR_DATA_EN (1 << 6) 110 #ifdef CONFIG_FTSDC010_SDIO 111 #define FTSDC010_DCR_FIFOTH (1 << 7) 112 #define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8) 113 #define FTSDC010_DCR_FIFO_RST (1 << 10) 114 #endif /* CONFIG_FTSDC010_SDIO */ 115 116 #define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */ 117 #define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */ 118 #define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */ 119 120 #define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */ 121 122 /* CPRM related define */ 123 #define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008 124 #define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010 125 126 /* 0x28 - status register */ 127 #define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0) 128 #define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1) 129 #define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2) 130 #define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3) 131 #define FTSDC010_STATUS_RSP_CRC_OK (1 << 4) 132 #define FTSDC010_STATUS_DATA_CRC_OK (1 << 5) 133 #define FTSDC010_STATUS_CMD_SEND (1 << 6) 134 #define FTSDC010_STATUS_DATA_END (1 << 7) 135 #define FTSDC010_STATUS_FIFO_URUN (1 << 8) 136 #define FTSDC010_STATUS_FIFO_ORUN (1 << 9) 137 #define FTSDC010_STATUS_CARD_CHANGE (1 << 10) 138 #define FTSDC010_STATUS_CARD_DETECT (1 << 11) 139 #define FTSDC010_STATUS_WRITE_PROT (1 << 12) 140 #ifdef CONFIG_FTSDC010_SDIO 141 #define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */ 142 #define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */ 143 #define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */ 144 #define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */ 145 #define FTSDC010_STATUS_DATA0_STATUS (1 << 17) 146 #endif /* CONFIG_FTSDC010_SDIO */ 147 #define FTSDC010_STATUS_RSP_ERROR \ 148 (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT) 149 #define FTSDC010_STATUS_RSP_MASK \ 150 (FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK) 151 #define FTSDC010_STATUS_DATA_ERROR \ 152 (FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT) 153 #define FTSDC010_STATUS_DATA_MASK \ 154 (FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \ 155 | FTSDC010_STATUS_DATA_END) 156 157 /* 0x2c - clear register */ 158 #define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0) 159 #define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1) 160 #define FTSDC010_CLR_RSP_TIMEOUT (1 << 2) 161 #define FTSDC010_CLR_DATA_TIMEOUT (1 << 3) 162 #define FTSDC010_CLR_RSP_CRC_OK (1 << 4) 163 #define FTSDC010_CLR_DATA_CRC_OK (1 << 5) 164 #define FTSDC010_CLR_CMD_SEND (1 << 6) 165 #define FTSDC010_CLR_DATA_END (1 << 7) 166 #define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */ 167 #define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */ 168 #define FTSDC010_CLR_CARD_CHANGE (1 << 10) 169 #ifdef CONFIG_FTSDC010_SDIO 170 #define FTSDC010_CLR_SDIO_IRPT (1 << 16) 171 #endif /* CONFIG_FTSDC010_SDIO */ 172 173 /* 0x30 - interrupt mask register */ 174 #define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0) 175 #define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1) 176 #define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2) 177 #define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3) 178 #define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4) 179 #define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5) 180 #define FTSDC010_INT_MASK_CMD_SEND (1 << 6) 181 #define FTSDC010_INT_MASK_DATA_END (1 << 7) 182 #define FTSDC010_INT_MASK_FIFO_URUN (1 << 8) 183 #define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9) 184 #define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10) 185 #ifdef CONFIG_FTSDC010_SDIO 186 #define FTSDC010_INT_MASK_CP_READY (1 << 13) 187 #define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14) 188 #define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15) 189 #define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16) 190 #define FTSDC010_STATUS_DATA0_STATUS (1 << 17) 191 #endif /* CONFIG_FTSDC010_SDIO */ 192 193 /* ? */ 194 #define FTSDC010_CARD_INSERT 0x0 195 #define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT 196 197 /* 0x34 - power control register */ 198 #define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0) 199 #define FTSDC010_PCR_POWER_ON (1 << 4) 200 201 /* 0x38 - clock control register */ 202 #define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0) 203 #define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */ 204 #define FTSDC010_CCR_CLK_DIS (1 << 8) 205 #define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */ 206 207 /* card type */ 208 #define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE 209 #define FTSDC010_CARD_TYPE_MMC 0x0 210 211 /* 0x3c - bus width register */ 212 #define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */ 213 #define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */ 214 #define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */ 215 #define FTSDC010_BWR_MODE_MASK (7 << 0) 216 #define FTSDC010_BWR_MODE_SHIFT (0) 217 #define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */ 218 #define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */ 219 #define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */ 220 #define FTSDC010_BWR_CAPS_MASK (3 << 3) 221 #define FTSDC010_BWR_CAPS_SHIFT (3) 222 #define FTSDC010_BWR_CARD_DETECT (1 << 5) 223 224 /* 0x44 or 0x9c - feature register */ 225 #define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff) 226 #define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8) 227 228 #define FTSDC010_FIFO_DEPTH_4 0x04 229 #define FTSDC010_FIFO_DEPTH_8 0x08 230 #define FTSDC010_FIFO_DEPTH_16 0x10 231 232 /* 0x48 or 0xa0 - revision register */ 233 #define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0) 234 #define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8) 235 #define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16) 236 237 #ifdef CONFIG_FTSDC010_SDIO 238 /* 0x44 - general purpose output */ 239 #define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0) 240 241 /* 0x6c - sdio control register 1 */ 242 #define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0) 243 #define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12) 244 #define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13) 245 #define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14) 246 #define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15) 247 248 /* 0x70 - sdio control register 2 */ 249 #define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0) 250 #define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1) 251 252 /* 0x74 - sdio status register */ 253 #define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff) 254 #define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef) 255 256 #endif /* CONFIG_FTSDC010_SDIO */ 257 258 #endif /* __FTSDC010_H */ 259