1 /* 2 * (C) Copyright 2009 Faraday Technology 3 * Po-Yu Chuang <ratbert@faraday-tech.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 /* 21 * Power Management Unit 22 */ 23 #ifndef __FTPMU010_H 24 #define __FTPMU010_H 25 26 #ifndef __ASSEMBLY__ 27 struct ftpmu010 { 28 unsigned int IDNMBR0; /* 0x00 */ 29 unsigned int reserved0; /* 0x04 */ 30 unsigned int OSCC; /* 0x08 */ 31 unsigned int PMODE; /* 0x0C */ 32 unsigned int PMCR; /* 0x10 */ 33 unsigned int PED; /* 0x14 */ 34 unsigned int PEDSR; /* 0x18 */ 35 unsigned int reserved1; /* 0x1C */ 36 unsigned int PMSR; /* 0x20 */ 37 unsigned int PGSR; /* 0x24 */ 38 unsigned int MFPSR; /* 0x28 */ 39 unsigned int MISC; /* 0x2C */ 40 unsigned int PDLLCR0; /* 0x30 */ 41 unsigned int PDLLCR1; /* 0x34 */ 42 unsigned int AHBMCLKOFF; /* 0x38 */ 43 unsigned int APBMCLKOFF; /* 0x3C */ 44 unsigned int DCSRCR0; /* 0x40 */ 45 unsigned int DCSRCR1; /* 0x44 */ 46 unsigned int DCSRCR2; /* 0x48 */ 47 unsigned int SDRAMHTC; /* 0x4C */ 48 unsigned int PSPR0; /* 0x50 */ 49 unsigned int PSPR1; /* 0x54 */ 50 unsigned int PSPR2; /* 0x58 */ 51 unsigned int PSPR3; /* 0x5C */ 52 unsigned int PSPR4; /* 0x60 */ 53 unsigned int PSPR5; /* 0x64 */ 54 unsigned int PSPR6; /* 0x68 */ 55 unsigned int PSPR7; /* 0x6C */ 56 unsigned int PSPR8; /* 0x70 */ 57 unsigned int PSPR9; /* 0x74 */ 58 unsigned int PSPR10; /* 0x78 */ 59 unsigned int PSPR11; /* 0x7C */ 60 unsigned int PSPR12; /* 0x80 */ 61 unsigned int PSPR13; /* 0x84 */ 62 unsigned int PSPR14; /* 0x88 */ 63 unsigned int PSPR15; /* 0x8C */ 64 unsigned int AHBDMA_RACCS; /* 0x90 */ 65 unsigned int reserved2; /* 0x94 */ 66 unsigned int reserved3; /* 0x98 */ 67 unsigned int JSS; /* 0x9C */ 68 unsigned int CFC_RACC; /* 0xA0 */ 69 unsigned int SSP1_RACC; /* 0xA4 */ 70 unsigned int UART1TX_RACC; /* 0xA8 */ 71 unsigned int UART1RX_RACC; /* 0xAC */ 72 unsigned int UART2TX_RACC; /* 0xB0 */ 73 unsigned int UART2RX_RACC; /* 0xB4 */ 74 unsigned int SDC_RACC; /* 0xB8 */ 75 unsigned int I2SAC97_RACC; /* 0xBC */ 76 unsigned int IRDATX_RACC; /* 0xC0 */ 77 unsigned int reserved4; /* 0xC4 */ 78 unsigned int USBD_RACC; /* 0xC8 */ 79 unsigned int IRDARX_RACC; /* 0xCC */ 80 unsigned int IRDA_RACC; /* 0xD0 */ 81 unsigned int ED0_RACC; /* 0xD4 */ 82 unsigned int ED1_RACC; /* 0xD8 */ 83 }; 84 #endif /* __ASSEMBLY__ */ 85 86 /* 87 * ID Number 0 Register 88 */ 89 #define FTPMU010_ID_A320A 0x03200000 90 #define FTPMU010_ID_A320C 0x03200010 91 #define FTPMU010_ID_A320D 0x03200030 92 93 /* 94 * OSC Control Register 95 */ 96 #define FTPMU010_OSCC_OSCH_TRI (1 << 11) 97 #define FTPMU010_OSCC_OSCH_STABLE (1 << 9) 98 #define FTPMU010_OSCC_OSCH_OFF (1 << 8) 99 100 #define FTPMU010_OSCC_OSCL_TRI (1 << 3) 101 #define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) 102 #define FTPMU010_OSCC_OSCL_STABLE (1 << 1) 103 #define FTPMU010_OSCC_OSCL_OFF (1 << 0) 104 105 /* 106 * Power Mode Register 107 */ 108 #define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) 109 #define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) 110 #define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) 111 #define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) 112 #define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) 113 #define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) 114 #define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) 115 #define FTPMU010_PMODE_FCS (1 << 2) 116 #define FTPMU010_PMODE_TURBO (1 << 1) 117 #define FTPMU010_PMODE_SLEEP (1 << 0) 118 119 /* 120 * Power Manager Status Register 121 */ 122 #define FTPMU010_PMSR_SMR (1 << 10) 123 124 #define FTPMU010_PMSR_RDH (1 << 2) 125 #define FTPMU010_PMSR_PH (1 << 1) 126 #define FTPMU010_PMSR_CKEHLOW (1 << 0) 127 128 /* 129 * Multi-Function Port Setting Register 130 */ 131 #define FTPMU010_MFPSR_DEBUGSEL (1 << 17) 132 #define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) 133 #define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) 134 #define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) 135 #define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) 136 #define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) 137 #define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) 138 #define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) 139 #define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) 140 #define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) 141 #define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) 142 #define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) 143 #define FTPMU010_MFPSR_AC97PINSEL (1 << 3) 144 #define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) 145 #define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) 146 147 /* 148 * PLL/DLL Control Register 0 149 * Note: 150 * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: 151 * Datasheet indicated it starts at bit #21 which was wrong. 152 * 2. FTPMU010_PDLLCR0_DLLFRAG: 153 * Datasheet indicated it has 2 bit which was wrong. 154 */ 155 #define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) 156 #define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) 157 #define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) 158 #define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) 159 #define FTPMU010_PDLLCR0_DLLDIS (1 << 16) 160 #define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) 161 #define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) 162 #define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) 163 #define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) 164 #define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) 165 166 /* 167 * SDRAM Signal Hold Time Control Register 168 */ 169 #define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) 170 #define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) 171 #define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) 172 #define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) 173 #define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) 174 #define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) 175 #define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) 176 #define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) 177 #define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) 178 #define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) 179 180 #ifndef __ASSEMBLY__ 181 void ftpmu010_32768osc_enable(void); 182 void ftpmu010_dlldis_disable(void); 183 void ftpmu010_mfpsr_diselect_dev(unsigned int dev); 184 void ftpmu010_mfpsr_select_dev(unsigned int dev); 185 void ftpmu010_sdram_clk_disable(unsigned int cr0); 186 void ftpmu010_sdramhtc_set(unsigned int val); 187 #endif 188 189 #ifdef __ASSEMBLY__ 190 #define FTPMU010_IDNMBR0 0x00 191 #define FTPMU010_reserved0 0x04 192 #define FTPMU010_OSCC 0x08 193 #define FTPMU010_PMODE 0x0C 194 #define FTPMU010_PMCR 0x10 195 #define FTPMU010_PED 0x14 196 #define FTPMU010_PEDSR 0x18 197 #define FTPMU010_reserved1 0x1C 198 #define FTPMU010_PMSR 0x20 199 #define FTPMU010_PGSR 0x24 200 #define FTPMU010_MFPSR 0x28 201 #define FTPMU010_MISC 0x2C 202 #define FTPMU010_PDLLCR0 0x30 203 #define FTPMU010_PDLLCR1 0x34 204 #define FTPMU010_AHBMCLKOFF 0x38 205 #define FTPMU010_APBMCLKOFF 0x3C 206 #define FTPMU010_DCSRCR0 0x40 207 #define FTPMU010_DCSRCR1 0x44 208 #define FTPMU010_DCSRCR2 0x48 209 #define FTPMU010_SDRAMHTC 0x4C 210 #define FTPMU010_PSPR0 0x50 211 #define FTPMU010_PSPR1 0x54 212 #define FTPMU010_PSPR2 0x58 213 #define FTPMU010_PSPR3 0x5C 214 #define FTPMU010_PSPR4 0x60 215 #define FTPMU010_PSPR5 0x64 216 #define FTPMU010_PSPR6 0x68 217 #define FTPMU010_PSPR7 0x6C 218 #define FTPMU010_PSPR8 0x70 219 #define FTPMU010_PSPR9 0x74 220 #define FTPMU010_PSPR10 0x78 221 #define FTPMU010_PSPR11 0x7C 222 #define FTPMU010_PSPR12 0x80 223 #define FTPMU010_PSPR13 0x84 224 #define FTPMU010_PSPR14 0x88 225 #define FTPMU010_PSPR15 0x8C 226 #define FTPMU010_AHBDMA_RACCS 0x90 227 #define FTPMU010_reserved2 0x94 228 #define FTPMU010_reserved3 0x98 229 #define FTPMU010_JSS 0x9C 230 #define FTPMU010_CFC_RACC 0xA0 231 #define FTPMU010_SSP1_RACC 0xA4 232 #define FTPMU010_UART1TX_RACC 0xA8 233 #define FTPMU010_UART1RX_RACC 0xAC 234 #define FTPMU010_UART2TX_RACC 0xB0 235 #define FTPMU010_UART2RX_RACC 0xB4 236 #define FTPMU010_SDC_RACC 0xB8 237 #define FTPMU010_I2SAC97_RACC 0xBC 238 #define FTPMU010_IRDATX_RACC 0xC0 239 #define FTPMU010_reserved4 0xC4 240 #define FTPMU010_USBD_RACC 0xC8 241 #define FTPMU010_IRDARX_RACC 0xCC 242 #define FTPMU010_IRDA_RACC 0xD0 243 #define FTPMU010_ED0_RACC 0xD4 244 #define FTPMU010_ED1_RACC 0xD8 245 #endif /* __ASSEMBLY__ */ 246 247 #endif /* __FTPMU010_H */ 248