1 /* 2 * Copyright 2003 Motorola,Inc. 3 * Xianghua Xiao(x.xiao@motorola.com) 4 */ 5 6 #ifndef __E500_H__ 7 #define __E500_H__ 8 9 #ifndef __ASSEMBLY__ 10 11 typedef struct 12 { 13 unsigned long freqProcessor; 14 unsigned long freqSystemBus; 15 unsigned long freqDDRBus; 16 } MPC85xx_SYS_INFO; 17 18 #endif /* _ASMLANGUAGE */ 19 20 /* Motorola E500 core provides 16 TLB1 entries; they can be used for 21 * initial memory mapping like legacy BAT registers do. Usually we 22 * use four MAS registers(MAS0-3) to operate on TLB1 entries. 23 * 24 * While there are 16 Entries with variable Page Sizes in TLB1, 25 * there are also 256 Entries with fixed 4K pages in TLB0. 26 * 27 * We also need LAWs(Local Access Window) to associate a range of 28 * the local 32-bit address space with a particular target interface 29 * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM. 30 * 31 * We put TLB1/LAW code here because memory mapping is board-specific 32 * instead of cpu-specific. 33 * 34 * While these macros are all nominally for TLB1 by name, they can 35 * also be used for TLB0 as well. 36 */ 37 38 39 /* 40 * Convert addresses to Effective and Real Page Numbers. 41 * Grab the high 20-bits and shift 'em down, dropping the "byte offset". 42 */ 43 #define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff) 44 #define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff) 45 46 47 /* MAS0 48 * tlbsel(TLB Select):0,1 49 * esel(Entry Select): 0,1,2,...,15 for TLB1 50 * nv(Next victim):0,1 51 */ 52 #define TLB1_MAS0(tlbsel,esel,nv) \ 53 ((((tlbsel) << 28) & MAS0_TLBSEL) |\ 54 (((esel) << 16) & MAS0_ESEL ) |\ 55 (nv) ) 56 57 58 /* MAS1 59 * v(TLB valid bit):0,1 60 * iprot(invalidate protect):0,1 61 * tid(translation identity):8bit to match process IDs 62 * ts(translation space,comparing with MSR[IS,DS]): 0,1 63 * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M) 64 */ 65 #define TLB1_MAS1(v,iprot,tid,ts,tsize) \ 66 ((((v) << 31) & MAS1_VALID) |\ 67 (((iprot) << 30) & MAS1_IPROT) |\ 68 (((tid) << 16) & MAS1_TID) |\ 69 (((ts) << 12) & MAS1_TS) |\ 70 (((tsize) << 8) & MAS1_TSIZE) ) 71 72 73 /* MAS2 74 * epn(effective page number):20bits 75 * sharen(Shared cache state):0,1 76 * x0,x1(implementation specific page attribute):0,1 77 * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded, 78 * endianness):0,1 79 */ 80 #define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \ 81 ((((epn) << 12) & MAS2_EPN) |\ 82 (((sharen) << 9) & MAS2_SHAREN) |\ 83 (((x0) << 6) & MAS2_X0) |\ 84 (((x1) << 5) & MAS2_X1) |\ 85 (((w) << 4) & MAS2_W) |\ 86 (((i) << 3) & MAS2_I) |\ 87 (((m) << 2) & MAS2_M) |\ 88 (((g) << 1) & MAS2_G) |\ 89 (e) ) 90 91 92 /* MAS3 93 * rpn(real page number):20bits 94 * u0-u3(user bits, useful for page table management in OS):0,1 95 * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read, 96 * write,execute permission). 97 */ 98 #define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \ 99 ((((rpn) << 12) & MAS3_RPN) |\ 100 (((u0) << 9) & MAS3_U0) |\ 101 (((u1) << 8) & MAS3_U1) |\ 102 (((u2) << 7) & MAS3_U2) |\ 103 (((u3) << 6) & MAS3_U3) |\ 104 (((ux) << 5) & MAS3_UX) |\ 105 (((sx) << 4) & MAS3_SX) |\ 106 (((uw) << 3) & MAS3_UW) |\ 107 (((sw) << 2) & MAS3_SW) |\ 108 (((ur) << 1) & MAS3_UR) |\ 109 (sr) ) 110 111 112 #define RESET_VECTOR 0xfffffffc 113 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache 114 line aligned data. */ 115 116 #endif /* __E500_H__ */ 117