1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012 SAMSUNG Electronics 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 */ 6 7 #ifndef __DWMMC_HW_H 8 #define __DWMMC_HW_H 9 10 #include <asm/io.h> 11 #include <mmc.h> 12 13 #define DWMCI_CTRL 0x000 14 #define DWMCI_PWREN 0x004 15 #define DWMCI_CLKDIV 0x008 16 #define DWMCI_CLKSRC 0x00C 17 #define DWMCI_CLKENA 0x010 18 #define DWMCI_TMOUT 0x014 19 #define DWMCI_CTYPE 0x018 20 #define DWMCI_BLKSIZ 0x01C 21 #define DWMCI_BYTCNT 0x020 22 #define DWMCI_INTMASK 0x024 23 #define DWMCI_CMDARG 0x028 24 #define DWMCI_CMD 0x02C 25 #define DWMCI_RESP0 0x030 26 #define DWMCI_RESP1 0x034 27 #define DWMCI_RESP2 0x038 28 #define DWMCI_RESP3 0x03C 29 #define DWMCI_MINTSTS 0x040 30 #define DWMCI_RINTSTS 0x044 31 #define DWMCI_STATUS 0x048 32 #define DWMCI_FIFOTH 0x04C 33 #define DWMCI_CDETECT 0x050 34 #define DWMCI_WRTPRT 0x054 35 #define DWMCI_GPIO 0x058 36 #define DWMCI_TCMCNT 0x05C 37 #define DWMCI_TBBCNT 0x060 38 #define DWMCI_DEBNCE 0x064 39 #define DWMCI_USRID 0x068 40 #define DWMCI_VERID 0x06C 41 #define DWMCI_HCON 0x070 42 #define DWMCI_UHS_REG 0x074 43 #define DWMCI_BMOD 0x080 44 #define DWMCI_PLDMND 0x084 45 #define DWMCI_DBADDR 0x088 46 #define DWMCI_IDSTS 0x08C 47 #define DWMCI_IDINTEN 0x090 48 #define DWMCI_DSCADDR 0x094 49 #define DWMCI_BUFADDR 0x098 50 #define DWMCI_DATA 0x200 51 52 /* Interrupt Mask register */ 53 #define DWMCI_INTMSK_ALL 0xffffffff 54 #define DWMCI_INTMSK_RE (1 << 1) 55 #define DWMCI_INTMSK_CDONE (1 << 2) 56 #define DWMCI_INTMSK_DTO (1 << 3) 57 #define DWMCI_INTMSK_TXDR (1 << 4) 58 #define DWMCI_INTMSK_RXDR (1 << 5) 59 #define DWMCI_INTMSK_DCRC (1 << 7) 60 #define DWMCI_INTMSK_RTO (1 << 8) 61 #define DWMCI_INTMSK_DRTO (1 << 9) 62 #define DWMCI_INTMSK_HTO (1 << 10) 63 #define DWMCI_INTMSK_FRUN (1 << 11) 64 #define DWMCI_INTMSK_HLE (1 << 12) 65 #define DWMCI_INTMSK_SBE (1 << 13) 66 #define DWMCI_INTMSK_ACD (1 << 14) 67 #define DWMCI_INTMSK_EBE (1 << 15) 68 69 /* Raw interrupt Regsiter */ 70 #define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ 71 DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) 72 #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) 73 /* CTRL register */ 74 #define DWMCI_CTRL_RESET (1 << 0) 75 #define DWMCI_CTRL_FIFO_RESET (1 << 1) 76 #define DWMCI_CTRL_DMA_RESET (1 << 2) 77 #define DWMCI_DMA_EN (1 << 5) 78 #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) 79 #define DWMCI_IDMAC_EN (1 << 25) 80 #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ 81 DWMCI_CTRL_DMA_RESET) 82 83 /* CMD register */ 84 #define DWMCI_CMD_RESP_EXP (1 << 6) 85 #define DWMCI_CMD_RESP_LENGTH (1 << 7) 86 #define DWMCI_CMD_CHECK_CRC (1 << 8) 87 #define DWMCI_CMD_DATA_EXP (1 << 9) 88 #define DWMCI_CMD_RW (1 << 10) 89 #define DWMCI_CMD_SEND_STOP (1 << 12) 90 #define DWMCI_CMD_ABORT_STOP (1 << 14) 91 #define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) 92 #define DWMCI_CMD_UPD_CLK (1 << 21) 93 #define DWMCI_CMD_USE_HOLD_REG (1 << 29) 94 #define DWMCI_CMD_START (1 << 31) 95 96 /* CLKENA register */ 97 #define DWMCI_CLKEN_ENABLE (1 << 0) 98 #define DWMCI_CLKEN_LOW_PWR (1 << 16) 99 100 /* Card-type registe */ 101 #define DWMCI_CTYPE_1BIT 0 102 #define DWMCI_CTYPE_4BIT (1 << 0) 103 #define DWMCI_CTYPE_8BIT (1 << 16) 104 105 /* Status Register */ 106 #define DWMCI_FIFO_EMPTY (1 << 2) 107 #define DWMCI_FIFO_FULL (1 << 3) 108 #define DWMCI_BUSY (1 << 9) 109 #define DWMCI_FIFO_MASK 0x1fff 110 #define DWMCI_FIFO_SHIFT 17 111 112 /* FIFOTH Register */ 113 #define MSIZE(x) ((x) << 28) 114 #define RX_WMARK(x) ((x) << 16) 115 #define TX_WMARK(x) (x) 116 #define RX_WMARK_SHIFT 16 117 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) 118 119 #define DWMCI_IDMAC_OWN (1 << 31) 120 #define DWMCI_IDMAC_CH (1 << 4) 121 #define DWMCI_IDMAC_FS (1 << 3) 122 #define DWMCI_IDMAC_LD (1 << 2) 123 124 /* Bus Mode Register */ 125 #define DWMCI_BMOD_IDMAC_RESET (1 << 0) 126 #define DWMCI_BMOD_IDMAC_FB (1 << 1) 127 #define DWMCI_BMOD_IDMAC_EN (1 << 7) 128 129 /* UHS register */ 130 #define DWMCI_DDR_MODE (1 << 16) 131 132 /* quirks */ 133 #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) 134 135 /** 136 * struct dwmci_host - Information about a designware MMC host 137 * 138 * @name: Device name 139 * @ioaddr: Base I/O address of controller 140 * @quirks: Quick flags - see DWMCI_QUIRK_... 141 * @caps: Capabilities - see MMC_MODE_... 142 * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL 143 * @div: Arbitrary clock divider value for use by controller 144 * @dev_index: Arbitrary device index for use by controller 145 * @dev_id: Arbitrary device ID for use by controller 146 * @buswidth: Bus width in bits (8 or 4) 147 * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) 148 * @mmc: Pointer to generic MMC structure for this device 149 * @priv: Private pointer for use by controller 150 */ 151 struct dwmci_host { 152 const char *name; 153 void *ioaddr; 154 unsigned int quirks; 155 unsigned int caps; 156 unsigned int version; 157 unsigned int clock; 158 unsigned int bus_hz; 159 unsigned int div; 160 int dev_index; 161 int dev_id; 162 int buswidth; 163 u32 fifoth_val; 164 struct mmc *mmc; 165 void *priv; 166 167 void (*clksel)(struct dwmci_host *host); 168 void (*board_init)(struct dwmci_host *host); 169 170 /** 171 * Get / set a particular MMC clock frequency 172 * 173 * This is used to request the current clock frequency of the clock 174 * that drives the DWMMC peripheral. The caller will then use this 175 * information to work out the divider it needs to achieve the 176 * required MMC bus clock frequency. If you want to handle the 177 * clock external to DWMMC, use @freq to select the frequency and 178 * return that value too. Then DWMMC will put itself in bypass mode. 179 * 180 * @host: DWMMC host 181 * @freq: Frequency the host is trying to achieve 182 */ 183 unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); 184 #ifndef CONFIG_BLK 185 struct mmc_config cfg; 186 #endif 187 188 /* use fifo mode to read and write data */ 189 bool fifo_mode; 190 }; 191 192 struct dwmci_idmac { 193 u32 flags; 194 u32 cnt; 195 u32 addr; 196 u32 next_addr; 197 } __aligned(ARCH_DMA_MINALIGN); 198 199 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) 200 { 201 writel(val, host->ioaddr + reg); 202 } 203 204 static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) 205 { 206 writew(val, host->ioaddr + reg); 207 } 208 209 static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) 210 { 211 writeb(val, host->ioaddr + reg); 212 } 213 static inline u32 dwmci_readl(struct dwmci_host *host, int reg) 214 { 215 return readl(host->ioaddr + reg); 216 } 217 218 static inline u16 dwmci_readw(struct dwmci_host *host, int reg) 219 { 220 return readw(host->ioaddr + reg); 221 } 222 223 static inline u8 dwmci_readb(struct dwmci_host *host, int reg) 224 { 225 return readb(host->ioaddr + reg); 226 } 227 228 #ifdef CONFIG_BLK 229 /** 230 * dwmci_setup_cfg() - Set up the configuration for DWMMC 231 * 232 * This is used to set up a DWMMC device when you are using CONFIG_BLK. 233 * 234 * This should be called from your MMC driver's probe() method once you have 235 * the information required. 236 * 237 * Generally your driver will have a platform data structure which holds both 238 * the configuration (struct mmc_config) and the MMC device info (struct mmc). 239 * For example: 240 * 241 * struct rockchip_mmc_plat { 242 * struct mmc_config cfg; 243 * struct mmc mmc; 244 * }; 245 * 246 * ... 247 * 248 * Inside U_BOOT_DRIVER(): 249 * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), 250 * 251 * To access platform data: 252 * struct rockchip_mmc_plat *plat = dev_get_platdata(dev); 253 * 254 * See rockchip_dw_mmc.c for an example. 255 * 256 * @cfg: Configuration structure to fill in (generally &plat->mmc) 257 * @host: DWMMC host 258 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) 259 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) 260 */ 261 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 262 u32 max_clk, u32 min_clk); 263 264 /** 265 * dwmci_bind() - Set up a new MMC block device 266 * 267 * This is used to set up a DWMMC block device when you are using CONFIG_BLK. 268 * It should be called from your driver's bind() method. 269 * 270 * See rockchip_dw_mmc.c for an example. 271 * 272 * @dev: Device to set up 273 * @mmc: Pointer to mmc structure (normally &plat->mmc) 274 * @cfg: Empty configuration structure (generally &plat->cfg). This is 275 * normally all zeroes at this point. The only purpose of passing 276 * this in is to set mmc->cfg to it. 277 * @return 0 if OK, -ve if the block device could not be created 278 */ 279 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); 280 281 #else 282 /** 283 * add_dwmci() - Add a new DWMMC interface 284 * 285 * This is used when you are not using CONFIG_BLK. Convert your driver over! 286 * 287 * @host: DWMMC host structure 288 * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) 289 * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) 290 * @return 0 if OK, -ve on error 291 */ 292 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); 293 #endif /* !CONFIG_BLK */ 294 295 #ifdef CONFIG_DM_MMC 296 /* Export the operations to drivers */ 297 int dwmci_probe(struct udevice *dev); 298 extern const struct dm_mmc_ops dm_dwmci_ops; 299 #endif 300 301 #endif /* __DWMMC_HW_H */ 302