183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cc232a9dSJernej Skrabec /* 3cc232a9dSJernej Skrabec * Copyright (c) 2015 Google, Inc 4cc232a9dSJernej Skrabec * Copyright 2014 Rockchip Inc. 5cc232a9dSJernej Skrabec * Copyright (C) 2011 Freescale Semiconductor, Inc. 6cc232a9dSJernej Skrabec * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 7cc232a9dSJernej Skrabec */ 8cc232a9dSJernej Skrabec 9cc232a9dSJernej Skrabec #ifndef _DW_HDMI_H 10cc232a9dSJernej Skrabec #define _DW_HDMI_H 11cc232a9dSJernej Skrabec 12cc232a9dSJernej Skrabec #include <edid.h> 13cc232a9dSJernej Skrabec 14cc232a9dSJernej Skrabec #define HDMI_EDID_BLOCK_SIZE 128 15cc232a9dSJernej Skrabec 16cc232a9dSJernej Skrabec /* Identification Registers */ 17cc232a9dSJernej Skrabec #define HDMI_DESIGN_ID 0x0000 18cc232a9dSJernej Skrabec #define HDMI_REVISION_ID 0x0001 19cc232a9dSJernej Skrabec #define HDMI_PRODUCT_ID0 0x0002 20cc232a9dSJernej Skrabec #define HDMI_PRODUCT_ID1 0x0003 21cc232a9dSJernej Skrabec #define HDMI_CONFIG0_ID 0x0004 22cc232a9dSJernej Skrabec #define HDMI_CONFIG1_ID 0x0005 23cc232a9dSJernej Skrabec #define HDMI_CONFIG2_ID 0x0006 24cc232a9dSJernej Skrabec #define HDMI_CONFIG3_ID 0x0007 25cc232a9dSJernej Skrabec 26cc232a9dSJernej Skrabec /* Interrupt Registers */ 27cc232a9dSJernej Skrabec #define HDMI_IH_FC_STAT0 0x0100 28cc232a9dSJernej Skrabec #define HDMI_IH_FC_STAT1 0x0101 29cc232a9dSJernej Skrabec #define HDMI_IH_FC_STAT2 0x0102 30cc232a9dSJernej Skrabec #define HDMI_IH_AS_STAT0 0x0103 31cc232a9dSJernej Skrabec #define HDMI_IH_PHY_STAT0 0x0104 32cc232a9dSJernej Skrabec #define HDMI_IH_I2CM_STAT0 0x0105 33cc232a9dSJernej Skrabec #define HDMI_IH_CEC_STAT0 0x0106 34cc232a9dSJernej Skrabec #define HDMI_IH_VP_STAT0 0x0107 35cc232a9dSJernej Skrabec #define HDMI_IH_I2CMPHY_STAT0 0x0108 36cc232a9dSJernej Skrabec #define HDMI_IH_AHBDMAAUD_STAT0 0x0109 37cc232a9dSJernej Skrabec 38cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_FC_STAT0 0x0180 39cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_FC_STAT1 0x0181 40cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_FC_STAT2 0x0182 41cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_AS_STAT0 0x0183 42cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_PHY_STAT0 0x0184 43cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_I2CM_STAT0 0x0185 44cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_CEC_STAT0 0x0186 45cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_VP_STAT0 0x0187 46cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 47cc232a9dSJernej Skrabec #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 48cc232a9dSJernej Skrabec #define HDMI_IH_MUTE 0x01FF 49cc232a9dSJernej Skrabec 50cc232a9dSJernej Skrabec /* Video Sample Registers */ 51cc232a9dSJernej Skrabec #define HDMI_TX_INVID0 0x0200 52cc232a9dSJernej Skrabec #define HDMI_TX_INSTUFFING 0x0201 53cc232a9dSJernej Skrabec #define HDMI_TX_GYDATA0 0x0202 54cc232a9dSJernej Skrabec #define HDMI_TX_GYDATA1 0x0203 55cc232a9dSJernej Skrabec #define HDMI_TX_RCRDATA0 0x0204 56cc232a9dSJernej Skrabec #define HDMI_TX_RCRDATA1 0x0205 57cc232a9dSJernej Skrabec #define HDMI_TX_BCBDATA0 0x0206 58cc232a9dSJernej Skrabec #define HDMI_TX_BCBDATA1 0x0207 59cc232a9dSJernej Skrabec 60cc232a9dSJernej Skrabec /* Video Packetizer Registers */ 61cc232a9dSJernej Skrabec #define HDMI_VP_STATUS 0x0800 62cc232a9dSJernej Skrabec #define HDMI_VP_PR_CD 0x0801 63cc232a9dSJernej Skrabec #define HDMI_VP_STUFF 0x0802 64cc232a9dSJernej Skrabec #define HDMI_VP_REMAP 0x0803 65cc232a9dSJernej Skrabec #define HDMI_VP_CONF 0x0804 66cc232a9dSJernej Skrabec #define HDMI_VP_STAT 0x0805 67cc232a9dSJernej Skrabec #define HDMI_VP_INT 0x0806 68cc232a9dSJernej Skrabec #define HDMI_VP_MASK 0x0807 69cc232a9dSJernej Skrabec #define HDMI_VP_POL 0x0808 70cc232a9dSJernej Skrabec 71cc232a9dSJernej Skrabec /* Frame Composer Registers */ 72cc232a9dSJernej Skrabec #define HDMI_FC_INVIDCONF 0x1000 73cc232a9dSJernej Skrabec #define HDMI_FC_INHACTV0 0x1001 74cc232a9dSJernej Skrabec #define HDMI_FC_INHACTV1 0x1002 75cc232a9dSJernej Skrabec #define HDMI_FC_INHBLANK0 0x1003 76cc232a9dSJernej Skrabec #define HDMI_FC_INHBLANK1 0x1004 77cc232a9dSJernej Skrabec #define HDMI_FC_INVACTV0 0x1005 78cc232a9dSJernej Skrabec #define HDMI_FC_INVACTV1 0x1006 79cc232a9dSJernej Skrabec #define HDMI_FC_INVBLANK 0x1007 80cc232a9dSJernej Skrabec #define HDMI_FC_HSYNCINDELAY0 0x1008 81cc232a9dSJernej Skrabec #define HDMI_FC_HSYNCINDELAY1 0x1009 82cc232a9dSJernej Skrabec #define HDMI_FC_HSYNCINWIDTH0 0x100A 83cc232a9dSJernej Skrabec #define HDMI_FC_HSYNCINWIDTH1 0x100B 84cc232a9dSJernej Skrabec #define HDMI_FC_VSYNCINDELAY 0x100C 85cc232a9dSJernej Skrabec #define HDMI_FC_VSYNCINWIDTH 0x100D 86cc232a9dSJernej Skrabec #define HDMI_FC_INFREQ0 0x100E 87cc232a9dSJernej Skrabec #define HDMI_FC_INFREQ1 0x100F 88cc232a9dSJernej Skrabec #define HDMI_FC_INFREQ2 0x1010 89cc232a9dSJernej Skrabec #define HDMI_FC_CTRLDUR 0x1011 90cc232a9dSJernej Skrabec #define HDMI_FC_EXCTRLDUR 0x1012 91cc232a9dSJernej Skrabec #define HDMI_FC_EXCTRLSPAC 0x1013 92cc232a9dSJernej Skrabec #define HDMI_FC_CH0PREAM 0x1014 93cc232a9dSJernej Skrabec #define HDMI_FC_CH1PREAM 0x1015 94cc232a9dSJernej Skrabec #define HDMI_FC_CH2PREAM 0x1016 95cc232a9dSJernej Skrabec #define HDMI_FC_AVICONF3 0x1017 96cc232a9dSJernej Skrabec #define HDMI_FC_GCP 0x1018 97cc232a9dSJernej Skrabec #define HDMI_FC_AVICONF0 0x1019 98cc232a9dSJernej Skrabec #define HDMI_FC_AVICONF1 0x101A 99cc232a9dSJernej Skrabec #define HDMI_FC_AVICONF2 0x101B 100cc232a9dSJernej Skrabec #define HDMI_FC_AVIVID 0x101C 101cc232a9dSJernej Skrabec #define HDMI_FC_AVIETB0 0x101D 102cc232a9dSJernej Skrabec #define HDMI_FC_AVIETB1 0x101E 103cc232a9dSJernej Skrabec #define HDMI_FC_AVISBB0 0x101F 104cc232a9dSJernej Skrabec #define HDMI_FC_AVISBB1 0x1020 105cc232a9dSJernej Skrabec #define HDMI_FC_AVIELB0 0x1021 106cc232a9dSJernej Skrabec #define HDMI_FC_AVIELB1 0x1022 107cc232a9dSJernej Skrabec #define HDMI_FC_AVISRB0 0x1023 108cc232a9dSJernej Skrabec #define HDMI_FC_AVISRB1 0x1024 109cc232a9dSJernej Skrabec #define HDMI_FC_AUDICONF0 0x1025 110cc232a9dSJernej Skrabec #define HDMI_FC_AUDICONF1 0x1026 111cc232a9dSJernej Skrabec #define HDMI_FC_AUDICONF2 0x1027 112cc232a9dSJernej Skrabec #define HDMI_FC_AUDICONF3 0x1028 113cc232a9dSJernej Skrabec #define HDMI_FC_VSDIEEEID0 0x1029 114cc232a9dSJernej Skrabec #define HDMI_FC_VSDSIZE 0x102A 115cc232a9dSJernej Skrabec 116cc232a9dSJernej Skrabec /* HDMI Source PHY Registers */ 117cc232a9dSJernej Skrabec #define HDMI_PHY_CONF0 0x3000 118cc232a9dSJernej Skrabec #define HDMI_PHY_TST0 0x3001 119cc232a9dSJernej Skrabec #define HDMI_PHY_TST1 0x3002 120cc232a9dSJernej Skrabec #define HDMI_PHY_TST2 0x3003 121cc232a9dSJernej Skrabec #define HDMI_PHY_STAT0 0x3004 122cc232a9dSJernej Skrabec #define HDMI_PHY_INT0 0x3005 123cc232a9dSJernej Skrabec #define HDMI_PHY_MASK0 0x3006 124cc232a9dSJernej Skrabec #define HDMI_PHY_POL0 0x3007 125cc232a9dSJernej Skrabec 126cc232a9dSJernej Skrabec /* HDMI Master PHY Registers */ 127cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 128cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 129cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 130cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 131cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 132cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 133cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 134cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_INT_ADDR 0x3027 135cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 136cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_DIV_ADDR 0x3029 137cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a 138cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b 139cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c 140cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d 141cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e 142cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f 143cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 144cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 145cc232a9dSJernej Skrabec #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 146cc232a9dSJernej Skrabec 147cc232a9dSJernej Skrabec /* Audio Sampler Registers */ 148cc232a9dSJernej Skrabec #define HDMI_AUD_CONF0 0x3100 149cc232a9dSJernej Skrabec #define HDMI_AUD_CONF1 0x3101 150cc232a9dSJernej Skrabec #define HDMI_AUD_INT 0x3102 151cc232a9dSJernej Skrabec #define HDMI_AUD_CONF2 0x3103 152cc232a9dSJernej Skrabec #define HDMI_AUD_INT1 0x3104 153cc232a9dSJernej Skrabec #define HDMI_AUD_N1 0x3200 154cc232a9dSJernej Skrabec #define HDMI_AUD_N2 0x3201 155cc232a9dSJernej Skrabec #define HDMI_AUD_N3 0x3202 156cc232a9dSJernej Skrabec #define HDMI_AUD_CTS1 0x3203 157cc232a9dSJernej Skrabec #define HDMI_AUD_CTS2 0x3204 158cc232a9dSJernej Skrabec #define HDMI_AUD_CTS3 0x3205 159cc232a9dSJernej Skrabec #define HDMI_AUD_INPUTCLKFS 0x3206 160cc232a9dSJernej Skrabec #define HDMI_AUD_SPDIFINT 0x3302 161cc232a9dSJernej Skrabec #define HDMI_AUD_CONF0_HBR 0x3400 162cc232a9dSJernej Skrabec #define HDMI_AUD_HBR_STATUS 0x3401 163cc232a9dSJernej Skrabec #define HDMI_AUD_HBR_INT 0x3402 164cc232a9dSJernej Skrabec #define HDMI_AUD_HBR_POL 0x3403 165cc232a9dSJernej Skrabec #define HDMI_AUD_HBR_MASK 0x3404 166cc232a9dSJernej Skrabec 167cc232a9dSJernej Skrabec /* Main Controller Registers */ 168cc232a9dSJernej Skrabec #define HDMI_MC_SFRDIV 0x4000 169cc232a9dSJernej Skrabec #define HDMI_MC_CLKDIS 0x4001 170cc232a9dSJernej Skrabec #define HDMI_MC_SWRSTZ 0x4002 171cc232a9dSJernej Skrabec #define HDMI_MC_OPCTRL 0x4003 172cc232a9dSJernej Skrabec #define HDMI_MC_FLOWCTRL 0x4004 173cc232a9dSJernej Skrabec #define HDMI_MC_PHYRSTZ 0x4005 174cc232a9dSJernej Skrabec #define HDMI_MC_LOCKONCLOCK 0x4006 175cc232a9dSJernej Skrabec #define HDMI_MC_HEACPHY_RST 0x4007 176cc232a9dSJernej Skrabec 177*56dd8d87SJorge Ramirez-Ortiz /* Color Space Converter Registers */ 178*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_CFG 0x4100 179*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_SCALE 0x4101 180*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A1_MSB 0x4102 181*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A1_LSB 0x4103 182*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A2_MSB 0x4104 183*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A2_LSB 0x4105 184*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A3_MSB 0x4106 185*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A3_LSB 0x4107 186*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A4_MSB 0x4108 187*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_A4_LSB 0x4109 188*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B1_MSB 0x410A 189*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B1_LSB 0x410B 190*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B2_MSB 0x410C 191*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B2_LSB 0x410D 192*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B3_MSB 0x410E 193*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B3_LSB 0x410F 194*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B4_MSB 0x4110 195*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_B4_LSB 0x4111 196*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C1_MSB 0x4112 197*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C1_LSB 0x4113 198*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C2_MSB 0x4114 199*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C2_LSB 0x4115 200*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C3_MSB 0x4116 201*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C3_LSB 0x4117 202*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C4_MSB 0x4118 203*56dd8d87SJorge Ramirez-Ortiz #define HDMI_CSC_COEF_C4_LSB 0x4119 204*56dd8d87SJorge Ramirez-Ortiz 205cc232a9dSJernej Skrabec /* I2C Master Registers (E-DDC) */ 206cc232a9dSJernej Skrabec #define HDMI_I2CM_SLAVE 0x7E00 207cc232a9dSJernej Skrabec #define HDMI_I2CM_ADDRESS 0x7E01 208cc232a9dSJernej Skrabec #define HDMI_I2CM_DATAO 0x7E02 209cc232a9dSJernej Skrabec #define HDMI_I2CM_DATAI 0x7E03 210cc232a9dSJernej Skrabec #define HDMI_I2CM_OPERATION 0x7E04 211cc232a9dSJernej Skrabec #define HDMI_I2CM_INT 0x7E05 212cc232a9dSJernej Skrabec #define HDMI_I2CM_CTLINT 0x7E06 213cc232a9dSJernej Skrabec #define HDMI_I2CM_DIV 0x7E07 214cc232a9dSJernej Skrabec #define HDMI_I2CM_SEGADDR 0x7E08 215cc232a9dSJernej Skrabec #define HDMI_I2CM_SOFTRSTZ 0x7E09 216cc232a9dSJernej Skrabec #define HDMI_I2CM_SEGPTR 0x7E0A 217cc232a9dSJernej Skrabec #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B 218cc232a9dSJernej Skrabec #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C 219cc232a9dSJernej Skrabec #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D 220cc232a9dSJernej Skrabec #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E 221cc232a9dSJernej Skrabec #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F 222cc232a9dSJernej Skrabec #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 223cc232a9dSJernej Skrabec #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 224cc232a9dSJernej Skrabec #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 225cc232a9dSJernej Skrabec #define HDMI_I2CM_BUF0 0x7E20 226cc232a9dSJernej Skrabec 227cc232a9dSJernej Skrabec enum { 228cc232a9dSJernej Skrabec /* HDMI PHY registers define */ 229cc232a9dSJernej Skrabec PHY_OPMODE_PLLCFG = 0x06, 230cc232a9dSJernej Skrabec PHY_CKCALCTRL = 0x05, 231cc232a9dSJernej Skrabec PHY_CKSYMTXCTRL = 0x09, 232cc232a9dSJernej Skrabec PHY_VLEVCTRL = 0x0e, 233cc232a9dSJernej Skrabec PHY_PLLCURRCTRL = 0x10, 234cc232a9dSJernej Skrabec PHY_PLLPHBYCTRL = 0x13, 235cc232a9dSJernej Skrabec PHY_PLLGMPCTRL = 0x15, 236cc232a9dSJernej Skrabec PHY_PLLCLKBISTPHASE = 0x17, 237cc232a9dSJernej Skrabec PHY_TXTERM = 0x19, 238cc232a9dSJernej Skrabec 239cc232a9dSJernej Skrabec /* ih_phy_stat0 field values */ 240cc232a9dSJernej Skrabec HDMI_IH_PHY_STAT0_HPD = 0x1, 241cc232a9dSJernej Skrabec 242cc232a9dSJernej Skrabec /* ih_mute field values */ 243cc232a9dSJernej Skrabec HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, 244cc232a9dSJernej Skrabec HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 245cc232a9dSJernej Skrabec 246cc232a9dSJernej Skrabec /* tx_invid0 field values */ 247cc232a9dSJernej Skrabec HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, 248cc232a9dSJernej Skrabec HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, 249cc232a9dSJernej Skrabec HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, 250cc232a9dSJernej Skrabec 251cc232a9dSJernej Skrabec /* tx_instuffing field values */ 252cc232a9dSJernej Skrabec HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, 253cc232a9dSJernej Skrabec HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, 254cc232a9dSJernej Skrabec HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 255cc232a9dSJernej Skrabec 256cc232a9dSJernej Skrabec /* vp_pr_cd field values */ 257cc232a9dSJernej Skrabec HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, 258cc232a9dSJernej Skrabec HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, 259cc232a9dSJernej Skrabec HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, 260cc232a9dSJernej Skrabec HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, 261cc232a9dSJernej Skrabec 262cc232a9dSJernej Skrabec /* vp_stuff field values */ 263cc232a9dSJernej Skrabec HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, 264cc232a9dSJernej Skrabec HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, 265cc232a9dSJernej Skrabec HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, 266cc232a9dSJernej Skrabec HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, 267cc232a9dSJernej Skrabec HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, 268cc232a9dSJernej Skrabec HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, 269cc232a9dSJernej Skrabec HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 270cc232a9dSJernej Skrabec HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 271cc232a9dSJernej Skrabec 272cc232a9dSJernej Skrabec /* vp_conf field values */ 273cc232a9dSJernej Skrabec HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, 274cc232a9dSJernej Skrabec HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, 275cc232a9dSJernej Skrabec HDMI_VP_CONF_PP_EN_ENMASK = 0x20, 276cc232a9dSJernej Skrabec HDMI_VP_CONF_PP_EN_DISABLE = 0x00, 277cc232a9dSJernej Skrabec HDMI_VP_CONF_PR_EN_MASK = 0x10, 278cc232a9dSJernej Skrabec HDMI_VP_CONF_PR_EN_DISABLE = 0x00, 279cc232a9dSJernej Skrabec HDMI_VP_CONF_YCC422_EN_MASK = 0x8, 280cc232a9dSJernej Skrabec HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, 281cc232a9dSJernej Skrabec HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, 282cc232a9dSJernej Skrabec HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, 283cc232a9dSJernej Skrabec HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, 284cc232a9dSJernej Skrabec HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, 285cc232a9dSJernej Skrabec 286cc232a9dSJernej Skrabec /* vp_remap field values */ 287cc232a9dSJernej Skrabec HDMI_VP_REMAP_YCC422_16BIT = 0x0, 288cc232a9dSJernej Skrabec 289cc232a9dSJernej Skrabec /* fc_invidconf field values */ 290cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, 291cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, 292cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, 293cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, 294cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, 295cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 296cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, 297cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, 298cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, 299cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, 300cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, 301cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, 302cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, 303cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, 304cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, 305cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, 306cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, 307cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, 308cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, 309cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, 310cc232a9dSJernej Skrabec HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, 311cc232a9dSJernej Skrabec 312cc232a9dSJernej Skrabec 313cc232a9dSJernej Skrabec /* fc_aviconf0-fc_aviconf3 field values */ 314cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, 315cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, 316cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, 317cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, 318cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, 319cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, 320cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, 321cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, 322cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, 323cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, 324cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, 325cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, 326cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, 327cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, 328cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, 329cc232a9dSJernej Skrabec HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, 330cc232a9dSJernej Skrabec 331cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, 332cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, 333cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, 334cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, 335cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, 336cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, 337cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, 338cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, 339cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, 340cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, 341cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, 342cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, 343cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, 344cc232a9dSJernej Skrabec HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, 345cc232a9dSJernej Skrabec 346cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_SCALING_MASK = 0x03, 347cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_SCALING_NONE = 0x00, 348cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, 349cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_SCALING_VERT = 0x02, 350cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, 351cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, 352cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, 353cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, 354cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, 355cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, 356cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, 357cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, 358cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, 359cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, 360cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, 361cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, 362cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, 363cc232a9dSJernej Skrabec HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, 364cc232a9dSJernej Skrabec 365cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, 366cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, 367cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, 368cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, 369cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, 370cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, 371cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, 372cc232a9dSJernej Skrabec HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, 373cc232a9dSJernej Skrabec 374cc232a9dSJernej Skrabec /* fc_gcp field values*/ 375cc232a9dSJernej Skrabec HDMI_FC_GCP_SET_AVMUTE = 0x02, 376cc232a9dSJernej Skrabec HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, 377cc232a9dSJernej Skrabec 378cc232a9dSJernej Skrabec /* phy_conf0 field values */ 379cc232a9dSJernej Skrabec HDMI_PHY_CONF0_PDZ_MASK = 0x80, 380cc232a9dSJernej Skrabec HDMI_PHY_CONF0_PDZ_OFFSET = 7, 381cc232a9dSJernej Skrabec HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, 382cc232a9dSJernej Skrabec HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, 383cc232a9dSJernej Skrabec HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, 384cc232a9dSJernej Skrabec HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, 385cc232a9dSJernej Skrabec HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, 386cc232a9dSJernej Skrabec HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, 387cc232a9dSJernej Skrabec HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, 388cc232a9dSJernej Skrabec HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, 389cc232a9dSJernej Skrabec HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, 390cc232a9dSJernej Skrabec HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, 391cc232a9dSJernej Skrabec HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, 392cc232a9dSJernej Skrabec HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, 393cc232a9dSJernej Skrabec 394cc232a9dSJernej Skrabec /* phy_tst0 field values */ 395cc232a9dSJernej Skrabec HDMI_PHY_TST0_TSTCLR_MASK = 0x20, 396cc232a9dSJernej Skrabec HDMI_PHY_TST0_TSTCLR_OFFSET = 5, 397cc232a9dSJernej Skrabec 398cc232a9dSJernej Skrabec /* phy_stat0 field values */ 399cc232a9dSJernej Skrabec HDMI_PHY_HPD = 0x02, 400cc232a9dSJernej Skrabec HDMI_PHY_TX_PHY_LOCK = 0x01, 401cc232a9dSJernej Skrabec 402cc232a9dSJernej Skrabec /* phy_i2cm_slave_addr field values */ 403cc232a9dSJernej Skrabec HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, 404cc232a9dSJernej Skrabec 405cc232a9dSJernej Skrabec /* phy_i2cm_operation_addr field values */ 406cc232a9dSJernej Skrabec HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, 407cc232a9dSJernej Skrabec 408cc232a9dSJernej Skrabec /* hdmi_phy_i2cm_int_addr */ 409cc232a9dSJernej Skrabec HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, 410cc232a9dSJernej Skrabec 411cc232a9dSJernej Skrabec /* hdmi_phy_i2cm_ctlint_addr */ 412cc232a9dSJernej Skrabec HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, 413cc232a9dSJernej Skrabec HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, 414cc232a9dSJernej Skrabec 415cc232a9dSJernej Skrabec /* aud_conf0 field values */ 416cc232a9dSJernej Skrabec HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, 417cc232a9dSJernej Skrabec HDMI_AUD_CONF0_I2S_SELECT = 0x20, 418cc232a9dSJernej Skrabec HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, 419cc232a9dSJernej Skrabec HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, 420cc232a9dSJernej Skrabec HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, 421cc232a9dSJernej Skrabec HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, 422cc232a9dSJernej Skrabec 423cc232a9dSJernej Skrabec /* aud_conf0 field values */ 424cc232a9dSJernej Skrabec HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, 425cc232a9dSJernej Skrabec HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, 426cc232a9dSJernej Skrabec 427cc232a9dSJernej Skrabec /* aud_n3 field values */ 428cc232a9dSJernej Skrabec HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, 429cc232a9dSJernej Skrabec HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, 430cc232a9dSJernej Skrabec 431cc232a9dSJernej Skrabec /* aud_cts3 field values */ 432cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, 433cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, 434cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_1 = 0, 435cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, 436cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, 437cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, 438cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, 439cc232a9dSJernej Skrabec HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, 440cc232a9dSJernej Skrabec HDMI_AUD_CTS3_CTS_MANUAL = 0x10, 441cc232a9dSJernej Skrabec HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, 442cc232a9dSJernej Skrabec 443cc232a9dSJernej Skrabec /* aud_inputclkfs filed values */ 444cc232a9dSJernej Skrabec HDMI_AUD_INPUTCLKFS_128 = 0x0, 445cc232a9dSJernej Skrabec 446cc232a9dSJernej Skrabec /* mc_clkdis field values */ 447*56dd8d87SJorge Ramirez-Ortiz HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, 448*56dd8d87SJorge Ramirez-Ortiz HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, 449*56dd8d87SJorge Ramirez-Ortiz HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, 450cc232a9dSJernej Skrabec HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, 451*56dd8d87SJorge Ramirez-Ortiz HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, 452cc232a9dSJernej Skrabec HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, 453cc232a9dSJernej Skrabec HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, 454cc232a9dSJernej Skrabec 455cc232a9dSJernej Skrabec /* mc_swrstz field values */ 456cc232a9dSJernej Skrabec HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, 457cc232a9dSJernej Skrabec HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, 458cc232a9dSJernej Skrabec 459cc232a9dSJernej Skrabec /* mc_flowctrl field values */ 460cc232a9dSJernej Skrabec HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, 461cc232a9dSJernej Skrabec HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, 462cc232a9dSJernej Skrabec 463cc232a9dSJernej Skrabec /* mc_phyrstz field values */ 464cc232a9dSJernej Skrabec HDMI_MC_PHYRSTZ_ASSERT = 0x0, 465cc232a9dSJernej Skrabec HDMI_MC_PHYRSTZ_DEASSERT = 0x1, 466cc232a9dSJernej Skrabec 467cc232a9dSJernej Skrabec /* mc_heacphy_rst field values */ 468cc232a9dSJernej Skrabec HDMI_MC_HEACPHY_RST_ASSERT = 0x1, 469cc232a9dSJernej Skrabec 470cc232a9dSJernej Skrabec /* i2cm filed values */ 471cc232a9dSJernej Skrabec HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, 472cc232a9dSJernej Skrabec HDMI_I2CM_SEGADDR_DDC = 0x30, 473cc232a9dSJernej Skrabec HDMI_I2CM_OP_RD8_EXT = 0x2, 474cc232a9dSJernej Skrabec HDMI_I2CM_OP_RD8 = 0x1, 475cc232a9dSJernej Skrabec HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, 476cc232a9dSJernej Skrabec HDMI_I2CM_DIV_FAST_MODE = 0x8, 477cc232a9dSJernej Skrabec HDMI_I2CM_DIV_STD_MODE = 0x0, 478cc232a9dSJernej Skrabec HDMI_I2CM_SOFTRSTZ_MASK = 0x1, 479*56dd8d87SJorge Ramirez-Ortiz 480*56dd8d87SJorge Ramirez-Ortiz /* CSC_CFG field values */ 481*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_INTMODE_MASK = 0x30, 482*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_INTMODE_OFFSET = 4, 483*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, 484*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, 485*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, 486*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_DECMODE_MASK = 0x3, 487*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_DECMODE_OFFSET = 0, 488*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, 489*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, 490*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, 491*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, 492*56dd8d87SJorge Ramirez-Ortiz 493*56dd8d87SJorge Ramirez-Ortiz /* CSC_SCALE field values */ 494*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, 495*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, 496*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, 497*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, 498*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, 499*56dd8d87SJorge Ramirez-Ortiz HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, 500cc232a9dSJernej Skrabec }; 501cc232a9dSJernej Skrabec 502cc232a9dSJernej Skrabec struct hdmi_mpll_config { 503cc232a9dSJernej Skrabec u64 mpixelclock; 504cc232a9dSJernej Skrabec /* Mode of Operation and PLL Dividers Control Register */ 505cc232a9dSJernej Skrabec u32 cpce; 506cc232a9dSJernej Skrabec /* PLL Gmp Control Register */ 507cc232a9dSJernej Skrabec u32 gmp; 508cc232a9dSJernej Skrabec /* PLL Current Control Register */ 509cc232a9dSJernej Skrabec u32 curr; 510cc232a9dSJernej Skrabec }; 511cc232a9dSJernej Skrabec 512cc232a9dSJernej Skrabec struct hdmi_phy_config { 513cc232a9dSJernej Skrabec u64 mpixelclock; 514cc232a9dSJernej Skrabec u32 sym_ctr; /* clock symbol and transmitter control */ 515cc232a9dSJernej Skrabec u32 term; /* transmission termination value */ 516cc232a9dSJernej Skrabec u32 vlev_ctr; /* voltage level control */ 517cc232a9dSJernej Skrabec }; 518cc232a9dSJernej Skrabec 519*56dd8d87SJorge Ramirez-Ortiz struct hdmi_vmode { 520*56dd8d87SJorge Ramirez-Ortiz bool mdataenablepolarity; 521*56dd8d87SJorge Ramirez-Ortiz 522*56dd8d87SJorge Ramirez-Ortiz unsigned int mpixelclock; 523*56dd8d87SJorge Ramirez-Ortiz unsigned int mpixelrepetitioninput; 524*56dd8d87SJorge Ramirez-Ortiz unsigned int mpixelrepetitionoutput; 525*56dd8d87SJorge Ramirez-Ortiz }; 526*56dd8d87SJorge Ramirez-Ortiz 527*56dd8d87SJorge Ramirez-Ortiz struct hdmi_data_info { 528*56dd8d87SJorge Ramirez-Ortiz unsigned int enc_in_bus_format; 529*56dd8d87SJorge Ramirez-Ortiz unsigned int enc_out_bus_format; 530*56dd8d87SJorge Ramirez-Ortiz unsigned int enc_in_encoding; 531*56dd8d87SJorge Ramirez-Ortiz unsigned int enc_out_encoding; 532*56dd8d87SJorge Ramirez-Ortiz unsigned int pix_repet_factor; 533*56dd8d87SJorge Ramirez-Ortiz unsigned int hdcp_enable; 534*56dd8d87SJorge Ramirez-Ortiz struct hdmi_vmode video_mode; 535*56dd8d87SJorge Ramirez-Ortiz }; 536*56dd8d87SJorge Ramirez-Ortiz 537cc232a9dSJernej Skrabec struct dw_hdmi { 538cc232a9dSJernej Skrabec ulong ioaddr; 539cc232a9dSJernej Skrabec const struct hdmi_mpll_config *mpll_cfg; 540cc232a9dSJernej Skrabec const struct hdmi_phy_config *phy_cfg; 541cc232a9dSJernej Skrabec u8 i2c_clk_high; 542cc232a9dSJernej Skrabec u8 i2c_clk_low; 543cc232a9dSJernej Skrabec u8 reg_io_width; 544*56dd8d87SJorge Ramirez-Ortiz struct hdmi_data_info hdmi_data; 545cc232a9dSJernej Skrabec 546cc232a9dSJernej Skrabec int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); 547fd998418SJorge Ramirez-Ortiz void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); 548fd998418SJorge Ramirez-Ortiz u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); 549cc232a9dSJernej Skrabec }; 550cc232a9dSJernej Skrabec 551cc232a9dSJernej Skrabec int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); 552cc232a9dSJernej Skrabec int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); 553cc232a9dSJernej Skrabec void dw_hdmi_phy_init(struct dw_hdmi *hdmi); 554cc232a9dSJernej Skrabec 555cc232a9dSJernej Skrabec int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); 556cc232a9dSJernej Skrabec int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); 557cc232a9dSJernej Skrabec void dw_hdmi_init(struct dw_hdmi *hdmi); 558cc232a9dSJernej Skrabec 559cc232a9dSJernej Skrabec #endif 560