1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 Google, Inc
4  */
5 
6 #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
7 #define _ABI_MACH_ASPEED_AST2500_RESET_H_
8 
9 /*
10  * The values are intentionally layed out as flags in
11  * WDT reset parameter.
12  */
13 
14 #define AST_RESET_SOC			0
15 #define AST_RESET_CHIP			1
16 #define AST_RESET_CPU			(1 << 1)
17 #define AST_RESET_ARM			(1 << 2)
18 #define AST_RESET_COPROC		(1 << 3)
19 #define AST_RESET_SDRAM			(1 << 4)
20 #define AST_RESET_AHB			(1 << 5)
21 #define AST_RESET_I2C			(1 << 6)
22 #define AST_RESET_MAC1			(1 << 7)
23 #define AST_RESET_MAC2			(1 << 8)
24 #define AST_RESET_GCRT			(1 << 9)
25 #define AST_RESET_USB20			(1 << 10)
26 #define AST_RESET_USB11_HOST		(1 << 11)
27 #define AST_RESET_USB11_HID		(1 << 12)
28 #define AST_RESET_VIDEO			(1 << 13)
29 #define AST_RESET_HAC			(1 << 14)
30 #define AST_RESET_LPC			(1 << 15)
31 #define AST_RESET_SDIO			(1 << 16)
32 #define AST_RESET_MIC			(1 << 17)
33 #define AST_RESET_CRT2D			(1 << 18)
34 #define AST_RESET_PWM			(1 << 19)
35 #define AST_RESET_PECI			(1 << 20)
36 #define AST_RESET_JTAG			(1 << 21)
37 #define AST_RESET_ADC			(1 << 22)
38 #define AST_RESET_GPIO			(1 << 23)
39 #define AST_RESET_MCTP			(1 << 24)
40 #define AST_RESET_XDMA			(1 << 25)
41 #define AST_RESET_SPI			(1 << 26)
42 #define AST_RESET_MISC			(1 << 27)
43 
44 #endif  /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
45