1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 Google, Inc 4 */ 5 6 #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_ 7 #define _ABI_MACH_ASPEED_AST2500_RESET_H_ 8 9 /* 10 * The values are intentionally layed out as flags in 11 * WDT reset parameter. 12 */ 13 #define ASPEED_RESET_CRT1 (37) 14 #define ASPEED_RESET_RESERVED36 (36) 15 #define ASPEED_RESET_RESERVED35 (35) 16 #define ASPEED_RESET_RESERVED34 (34) 17 #define ASPEED_RESET_RESERVED33 (33) 18 #define ASPEED_RESET_RESERVED32 (32) 19 20 #define ASPEED_RESET_RESERVED31 (31) 21 #define ASPEED_RESET_RESERVED30 (30) 22 #define ASPEED_RESET_RESERVED29 (29) 23 #define ASPEED_RESET_RESERVED28 (28) 24 #define ASPEED_RESET_RESERVED27 (27) 25 #define ASPEED_RESET_RESERVED26 (26) 26 #define ASPEED_RESET_XDMA (25) 27 #define ASPEED_RESET_MCTP (24) 28 #define ASPEED_RESET_ADC (23) 29 #define ASPEED_RESET_JTAG_MASTER (22) 30 #define ASPEED_RESET_RESERVED21 (21) 31 #define ASPEED_RESET_RESERVED20 (20) 32 #define ASPEED_RESET_RESERVED19 (19) 33 #define ASPEED_RESET_MIC (18) 34 #define ASPEED_RESET_RESERVED17 (17) 35 #define ASEPPD_RESET_SDIO (16) 36 #define ASPEED_RESET_UHCI (15) 37 #define ASPEED_RESET_EHCI_P1 (14) 38 #define ASPEED_RESET_CRT (13) 39 #define ASPEED_RESET_MAC2 (12) 40 #define ASPEED_RESET_MAC1 (11) 41 #define ASPEED_RESET_PECI (10) 42 #define ASPEED_RESET_PWM (9) 43 #define ASPEED_RESET_PCI_VGA (8) 44 #define ASPEED_RESET_2D (7) 45 #define ASPEED_RESET_VIDEO (6) 46 #define ASPEED_RESET_LPC_ESPI (5) 47 #define ASPEED_RESET_HACE (4) 48 #define ASPEED_RESET_EHCI_P2 (3) 49 #define ASPEED_RESET_I2C (2) 50 #define ASPEED_RESET_AHB (1) 51 #define ASPEED_RESET_SDRAM (0) 52 53 #endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */ 54