1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2c93adc08Smaxims@google.com /*
3c93adc08Smaxims@google.com  * Copyright 2017 Google, Inc
4c93adc08Smaxims@google.com  */
5c93adc08Smaxims@google.com 
6c93adc08Smaxims@google.com #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
7c93adc08Smaxims@google.com #define _ABI_MACH_ASPEED_AST2500_RESET_H_
8c93adc08Smaxims@google.com 
9c93adc08Smaxims@google.com /*
10c93adc08Smaxims@google.com  * The values are intentionally layed out as flags in
11c93adc08Smaxims@google.com  * WDT reset parameter.
12c93adc08Smaxims@google.com  */
13c93adc08Smaxims@google.com 
14c93adc08Smaxims@google.com #define AST_RESET_SOC			0
15c93adc08Smaxims@google.com #define AST_RESET_CHIP			1
16c93adc08Smaxims@google.com #define AST_RESET_CPU			(1 << 1)
17c93adc08Smaxims@google.com #define AST_RESET_ARM			(1 << 2)
18c93adc08Smaxims@google.com #define AST_RESET_COPROC		(1 << 3)
19c93adc08Smaxims@google.com #define AST_RESET_SDRAM			(1 << 4)
20c93adc08Smaxims@google.com #define AST_RESET_AHB			(1 << 5)
21c93adc08Smaxims@google.com #define AST_RESET_I2C			(1 << 6)
22c93adc08Smaxims@google.com #define AST_RESET_MAC1			(1 << 7)
23c93adc08Smaxims@google.com #define AST_RESET_MAC2			(1 << 8)
24c93adc08Smaxims@google.com #define AST_RESET_GCRT			(1 << 9)
25c93adc08Smaxims@google.com #define AST_RESET_USB20			(1 << 10)
26c93adc08Smaxims@google.com #define AST_RESET_USB11_HOST		(1 << 11)
27c93adc08Smaxims@google.com #define AST_RESET_USB11_HID		(1 << 12)
28c93adc08Smaxims@google.com #define AST_RESET_VIDEO			(1 << 13)
29c93adc08Smaxims@google.com #define AST_RESET_HAC			(1 << 14)
30c93adc08Smaxims@google.com #define AST_RESET_LPC			(1 << 15)
31c93adc08Smaxims@google.com #define AST_RESET_SDIO			(1 << 16)
32c93adc08Smaxims@google.com #define AST_RESET_MIC			(1 << 17)
33c93adc08Smaxims@google.com #define AST_RESET_CRT2D			(1 << 18)
34c93adc08Smaxims@google.com #define AST_RESET_PWM			(1 << 19)
35c93adc08Smaxims@google.com #define AST_RESET_PECI			(1 << 20)
36c93adc08Smaxims@google.com #define AST_RESET_JTAG			(1 << 21)
37c93adc08Smaxims@google.com #define AST_RESET_ADC			(1 << 22)
38c93adc08Smaxims@google.com #define AST_RESET_GPIO			(1 << 23)
39c93adc08Smaxims@google.com #define AST_RESET_MCTP			(1 << 24)
40c93adc08Smaxims@google.com #define AST_RESET_XDMA			(1 << 25)
41c93adc08Smaxims@google.com #define AST_RESET_SPI			(1 << 26)
42c93adc08Smaxims@google.com #define AST_RESET_MISC			(1 << 27)
43c93adc08Smaxims@google.com 
44c93adc08Smaxims@google.com #endif  /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
45