1 /* 2 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 8 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 9 10 /* MPUMODRST */ 11 #define CPU0_RESET 0 12 #define CPU1_RESET 1 13 #define WDS_RESET 2 14 #define SCUPER_RESET 3 15 #define L2_RESET 4 16 17 /* PERMODRST */ 18 #define EMAC0_RESET 32 19 #define EMAC1_RESET 33 20 #define USB0_RESET 34 21 #define USB1_RESET 35 22 #define NAND_RESET 36 23 #define QSPI_RESET 37 24 #define L4WD0_RESET 38 25 #define L4WD1_RESET 39 26 #define OSC1TIMER0_RESET 40 27 #define OSC1TIMER1_RESET 41 28 #define SPTIMER0_RESET 42 29 #define SPTIMER1_RESET 43 30 #define I2C0_RESET 44 31 #define I2C1_RESET 45 32 #define I2C2_RESET 46 33 #define I2C3_RESET 47 34 #define UART0_RESET 48 35 #define UART1_RESET 49 36 #define SPIM0_RESET 50 37 #define SPIM1_RESET 51 38 #define SPIS0_RESET 52 39 #define SPIS1_RESET 53 40 #define SDMMC_RESET 54 41 #define CAN0_RESET 55 42 #define CAN1_RESET 56 43 #define GPIO0_RESET 57 44 #define GPIO1_RESET 58 45 #define GPIO2_RESET 59 46 #define DMA_RESET 60 47 #define SDR_RESET 61 48 49 /* PER2MODRST */ 50 #define DMAIF0_RESET 64 51 #define DMAIF1_RESET 65 52 #define DMAIF2_RESET 66 53 #define DMAIF3_RESET 67 54 #define DMAIF4_RESET 68 55 #define DMAIF5_RESET 69 56 #define DMAIF6_RESET 70 57 #define DMAIF7_RESET 71 58 59 /* BRGMODRST */ 60 #define HPS2FPGA_RESET 96 61 #define LWHPS2FPGA_RESET 97 62 #define FPGA2HPS_RESET 98 63 64 /* MISCMODRST*/ 65 #define ROM_RESET 128 66 #define OCRAM_RESET 129 67 #define SYSMGR_RESET 130 68 #define SYSMGRCOLD_RESET 131 69 #define FPGAMGR_RESET 132 70 #define ACPIDMAP_RESET 133 71 #define S2F_RESET 134 72 #define S2FCOLD_RESET 135 73 #define NRSTPIN_RESET 136 74 #define TIMESTAMPCOLD_RESET 137 75 #define CLKMGRCOLD_RESET 138 76 #define SCANMGR_RESET 139 77 #define FRZCTRLCOLD_RESET 140 78 #define SYSDBG_RESET 141 79 #define DBG_RESET 142 80 #define TAPCOLD_RESET 143 81 #define SDRCOLD_RESET 144 82 83 #endif 84