1*50e031efSMarek Vasut /* SPDX-License-Identifier: GPL-2.0 */ 2*50e031efSMarek Vasut /* 3*50e031efSMarek Vasut * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 4*50e031efSMarek Vasut * Copyright (C) 2016 Glider bvba 5*50e031efSMarek Vasut */ 6*50e031efSMarek Vasut 7*50e031efSMarek Vasut #ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ 8*50e031efSMarek Vasut #define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ 9*50e031efSMarek Vasut 10*50e031efSMarek Vasut /* 11*50e031efSMarek Vasut * These power domain indices match the numbers of the interrupt bits 12*50e031efSMarek Vasut * representing the power areas in the various Interrupt Registers 13*50e031efSMarek Vasut * (e.g. SYSCISR, Interrupt Status Register) 14*50e031efSMarek Vasut */ 15*50e031efSMarek Vasut 16*50e031efSMarek Vasut #define R8A77965_PD_CA57_CPU0 0 17*50e031efSMarek Vasut #define R8A77965_PD_CA57_CPU1 1 18*50e031efSMarek Vasut #define R8A77965_PD_A3VP 9 19*50e031efSMarek Vasut #define R8A77965_PD_CA57_SCU 12 20*50e031efSMarek Vasut #define R8A77965_PD_CR7 13 21*50e031efSMarek Vasut #define R8A77965_PD_A3VC 14 22*50e031efSMarek Vasut #define R8A77965_PD_3DG_A 17 23*50e031efSMarek Vasut #define R8A77965_PD_3DG_B 18 24*50e031efSMarek Vasut #define R8A77965_PD_A3IR 24 25*50e031efSMarek Vasut #define R8A77965_PD_A2VC1 26 26*50e031efSMarek Vasut 27*50e031efSMarek Vasut /* Always-on power area */ 28*50e031efSMarek Vasut #define R8A77965_PD_ALWAYS_ON 32 29*50e031efSMarek Vasut 30*50e031efSMarek Vasut #endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ 31