1*ee562dc3SStephen Warren #ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H 2*ee562dc3SStephen Warren #define DT_BINDINGS_MEMORY_TEGRA210_MC_H 3*ee562dc3SStephen Warren 4*ee562dc3SStephen Warren #define TEGRA_SWGROUP_PTC 0 5*ee562dc3SStephen Warren #define TEGRA_SWGROUP_DC 1 6*ee562dc3SStephen Warren #define TEGRA_SWGROUP_DCB 2 7*ee562dc3SStephen Warren #define TEGRA_SWGROUP_AFI 3 8*ee562dc3SStephen Warren #define TEGRA_SWGROUP_AVPC 4 9*ee562dc3SStephen Warren #define TEGRA_SWGROUP_HDA 5 10*ee562dc3SStephen Warren #define TEGRA_SWGROUP_HC 6 11*ee562dc3SStephen Warren #define TEGRA_SWGROUP_NVENC 7 12*ee562dc3SStephen Warren #define TEGRA_SWGROUP_PPCS 8 13*ee562dc3SStephen Warren #define TEGRA_SWGROUP_SATA 9 14*ee562dc3SStephen Warren #define TEGRA_SWGROUP_MPCORE 10 15*ee562dc3SStephen Warren #define TEGRA_SWGROUP_ISP2 11 16*ee562dc3SStephen Warren #define TEGRA_SWGROUP_XUSB_HOST 12 17*ee562dc3SStephen Warren #define TEGRA_SWGROUP_XUSB_DEV 13 18*ee562dc3SStephen Warren #define TEGRA_SWGROUP_ISP2B 14 19*ee562dc3SStephen Warren #define TEGRA_SWGROUP_TSEC 15 20*ee562dc3SStephen Warren #define TEGRA_SWGROUP_A9AVP 16 21*ee562dc3SStephen Warren #define TEGRA_SWGROUP_GPU 17 22*ee562dc3SStephen Warren #define TEGRA_SWGROUP_SDMMC1A 18 23*ee562dc3SStephen Warren #define TEGRA_SWGROUP_SDMMC2A 19 24*ee562dc3SStephen Warren #define TEGRA_SWGROUP_SDMMC3A 20 25*ee562dc3SStephen Warren #define TEGRA_SWGROUP_SDMMC4A 21 26*ee562dc3SStephen Warren #define TEGRA_SWGROUP_VIC 22 27*ee562dc3SStephen Warren #define TEGRA_SWGROUP_VI 23 28*ee562dc3SStephen Warren #define TEGRA_SWGROUP_NVDEC 24 29*ee562dc3SStephen Warren #define TEGRA_SWGROUP_APE 25 30*ee562dc3SStephen Warren #define TEGRA_SWGROUP_NVJPG 26 31*ee562dc3SStephen Warren #define TEGRA_SWGROUP_SE 27 32*ee562dc3SStephen Warren #define TEGRA_SWGROUP_AXIAP 28 33*ee562dc3SStephen Warren #define TEGRA_SWGROUP_ETR 29 34*ee562dc3SStephen Warren #define TEGRA_SWGROUP_TSECB 30 35*ee562dc3SStephen Warren 36*ee562dc3SStephen Warren #endif 37