1*6c9a1003SVikas Manocha #ifndef DT_BINDINGS_STM32_SDRAM_H 2*6c9a1003SVikas Manocha #define DT_BINDINGS_STM32_SDRAM_H 3*6c9a1003SVikas Manocha 4*6c9a1003SVikas Manocha #define NO_COL_8 0x0 5*6c9a1003SVikas Manocha #define NO_COL_9 0x1 6*6c9a1003SVikas Manocha #define NO_COL_10 0x2 7*6c9a1003SVikas Manocha #define NO_COL_11 0x3 8*6c9a1003SVikas Manocha 9*6c9a1003SVikas Manocha #define NO_ROW_11 0x0 10*6c9a1003SVikas Manocha #define NO_ROW_12 0x1 11*6c9a1003SVikas Manocha #define NO_ROW_13 0x2 12*6c9a1003SVikas Manocha 13*6c9a1003SVikas Manocha #define MWIDTH_8 0x0 14*6c9a1003SVikas Manocha #define MWIDTH_16 0x1 15*6c9a1003SVikas Manocha #define MWIDTH_32 0x2 16*6c9a1003SVikas Manocha #define BANKS_2 0x0 17*6c9a1003SVikas Manocha #define BANKS_4 0x1 18*6c9a1003SVikas Manocha #define CAS_1 0x1 19*6c9a1003SVikas Manocha #define CAS_2 0x2 20*6c9a1003SVikas Manocha #define CAS_3 0x3 21*6c9a1003SVikas Manocha #define RD_BURST_EN 0x1 22*6c9a1003SVikas Manocha #define RD_BURST_DIS 0x0 23*6c9a1003SVikas Manocha #define RD_PIPE_DL_0 0x0 24*6c9a1003SVikas Manocha #define RD_PIPE_DL_1 0x1 25*6c9a1003SVikas Manocha #define RD_PIPE_DL_2 0x2 26*6c9a1003SVikas Manocha 27*6c9a1003SVikas Manocha #define TMRD_1 0x1 28*6c9a1003SVikas Manocha #define TXSR_60 60 29*6c9a1003SVikas Manocha #define TRAS_42 42 30*6c9a1003SVikas Manocha #define TRC_60 60 31*6c9a1003SVikas Manocha #define TRP_18 18 32*6c9a1003SVikas Manocha #define TRCD_18 18 33*6c9a1003SVikas Manocha 34*6c9a1003SVikas Manocha #endif 35