13335786aSStefan Roese /* 23335786aSStefan Roese * Copyright (C) 2015-2016 Marvell International Ltd. 33335786aSStefan Roese * 43335786aSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 53335786aSStefan Roese */ 63335786aSStefan Roese 73335786aSStefan Roese #ifndef _COMPHY_DATA_H_ 83335786aSStefan Roese #define _COMPHY_DATA_H_ 93335786aSStefan Roese 103335786aSStefan Roese #define PHY_SPEED_1_25G 0 113335786aSStefan Roese #define PHY_SPEED_1_5G 1 123335786aSStefan Roese #define PHY_SPEED_2_5G 2 133335786aSStefan Roese #define PHY_SPEED_3G 3 143335786aSStefan Roese #define PHY_SPEED_3_125G 4 153335786aSStefan Roese #define PHY_SPEED_5G 5 16*b617a0d7SIgal Liberman #define PHY_SPEED_5_15625G 6 17*b617a0d7SIgal Liberman #define PHY_SPEED_6G 7 18*b617a0d7SIgal Liberman #define PHY_SPEED_6_25G 8 19*b617a0d7SIgal Liberman #define PHY_SPEED_10_3125G 9 20*b617a0d7SIgal Liberman #define PHY_SPEED_MAX 10 213335786aSStefan Roese #define PHY_SPEED_INVALID 0xff 223335786aSStefan Roese 233335786aSStefan Roese #define PHY_TYPE_UNCONNECTED 0 243335786aSStefan Roese #define PHY_TYPE_PEX0 1 253335786aSStefan Roese #define PHY_TYPE_PEX1 2 263335786aSStefan Roese #define PHY_TYPE_PEX2 3 273335786aSStefan Roese #define PHY_TYPE_PEX3 4 283335786aSStefan Roese #define PHY_TYPE_SATA0 5 293335786aSStefan Roese #define PHY_TYPE_SATA1 6 303335786aSStefan Roese #define PHY_TYPE_SATA2 7 313335786aSStefan Roese #define PHY_TYPE_SATA3 8 323335786aSStefan Roese #define PHY_TYPE_SGMII0 9 333335786aSStefan Roese #define PHY_TYPE_SGMII1 10 343335786aSStefan Roese #define PHY_TYPE_SGMII2 11 353335786aSStefan Roese #define PHY_TYPE_SGMII3 12 363335786aSStefan Roese #define PHY_TYPE_QSGMII 13 373335786aSStefan Roese #define PHY_TYPE_USB3_HOST0 14 383335786aSStefan Roese #define PHY_TYPE_USB3_HOST1 15 393335786aSStefan Roese #define PHY_TYPE_USB3_DEVICE 16 403335786aSStefan Roese #define PHY_TYPE_XAUI0 17 413335786aSStefan Roese #define PHY_TYPE_XAUI1 18 423335786aSStefan Roese #define PHY_TYPE_XAUI2 19 433335786aSStefan Roese #define PHY_TYPE_XAUI3 20 443335786aSStefan Roese #define PHY_TYPE_RXAUI0 21 453335786aSStefan Roese #define PHY_TYPE_RXAUI1 22 46cb686454SStefan Roese #define PHY_TYPE_SFI 23 476ecc0b1cSStefan Roese #define PHY_TYPE_IGNORE 24 486ecc0b1cSStefan Roese #define PHY_TYPE_MAX 25 493335786aSStefan Roese #define PHY_TYPE_INVALID 0xff 503335786aSStefan Roese 513335786aSStefan Roese #define PHY_POLARITY_NO_INVERT 0 523335786aSStefan Roese #define PHY_POLARITY_TXD_INVERT 1 533335786aSStefan Roese #define PHY_POLARITY_RXD_INVERT 2 543335786aSStefan Roese #define PHY_POLARITY_ALL_INVERT \ 553335786aSStefan Roese (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) 563335786aSStefan Roese 57e89acc4bSStefan Roese #define UTMI_PHY_TO_USB3_HOST0 0 58e89acc4bSStefan Roese #define UTMI_PHY_TO_USB3_HOST1 1 59e89acc4bSStefan Roese #define UTMI_PHY_TO_USB3_DEVICE0 2 603335786aSStefan Roese #define UTMI_PHY_INVALID 0xff 613335786aSStefan Roese 623335786aSStefan Roese #endif /* _COMPHY_DATA_H_ */ 633335786aSStefan Roese 64