1 /*
2  * This header provides constants for binding nvidia,tegra124-car.
3  *
4  * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7  * this case, those clocks are assigned IDs above 185 in order to highlight
8  * this issue. Implementations that interpret these clock IDs as bit values
9  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10  * explicitly handle these special cases.
11  *
12  * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
13  * above.
14  */
15 
16 #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
17 #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
18 
19 /* 0 */
20 /* 1 */
21 /* 2 */
22 #define TEGRA124_CLK_ISPB 3
23 #define TEGRA124_CLK_RTC 4
24 #define TEGRA124_CLK_TIMER 5
25 #define TEGRA124_CLK_UARTA 6
26 /* 7 (register bit affects uartb and vfir) */
27 /* 8 */
28 #define TEGRA124_CLK_SDMMC2 9
29 /* 10 (register bit affects spdif_in and spdif_out) */
30 #define TEGRA124_CLK_I2S1 11
31 #define TEGRA124_CLK_I2C1 12
32 #define TEGRA124_CLK_NDFLASH 13
33 #define TEGRA124_CLK_SDMMC1 14
34 #define TEGRA124_CLK_SDMMC4 15
35 /* 16 */
36 #define TEGRA124_CLK_PWM 17
37 #define TEGRA124_CLK_I2S2 18
38 /* 20 (register bit affects vi and vi_sensor) */
39 /* 21 */
40 #define TEGRA124_CLK_USBD 22
41 #define TEGRA124_CLK_ISP 23
42 /* 26 */
43 /* 25 */
44 #define TEGRA124_CLK_DISP2 26
45 #define TEGRA124_CLK_DISP1 27
46 #define TEGRA124_CLK_HOST1X 28
47 #define TEGRA124_CLK_VCP 29
48 #define TEGRA124_CLK_I2S0 30
49 /* 31 */
50 
51 /* 32 */
52 /* 33 */
53 #define TEGRA124_CLK_APBDMA 34
54 /* 35 */
55 #define TEGRA124_CLK_KBC 36
56 /* 37 */
57 /* 38 */
58 /* 39 (register bit affects fuse and fuse_burn) */
59 #define TEGRA124_CLK_KFUSE 40
60 #define TEGRA124_CLK_SBC1 41
61 #define TEGRA124_CLK_NOR 42
62 /* 43 */
63 #define TEGRA124_CLK_SBC2 44
64 /* 45 */
65 #define TEGRA124_CLK_SBC3 46
66 #define TEGRA124_CLK_I2C5 47
67 #define TEGRA124_CLK_DSIA 48
68 /* 49 */
69 #define TEGRA124_CLK_MIPI 50
70 #define TEGRA124_CLK_HDMI 51
71 #define TEGRA124_CLK_CSI 52
72 /* 53 */
73 #define TEGRA124_CLK_I2C2 54
74 #define TEGRA124_CLK_UARTC 55
75 #define TEGRA124_CLK_MIPI_CAL 56
76 #define TEGRA124_CLK_EMC 57
77 #define TEGRA124_CLK_USB2 58
78 #define TEGRA124_CLK_USB3 59
79 /* 60 */
80 #define TEGRA124_CLK_VDE 61
81 #define TEGRA124_CLK_BSEA 62
82 #define TEGRA124_CLK_BSEV 63
83 
84 /* 64 */
85 #define TEGRA124_CLK_UARTD 65
86 #define TEGRA124_CLK_UARTE 66
87 #define TEGRA124_CLK_I2C3 67
88 #define TEGRA124_CLK_SBC4 68
89 #define TEGRA124_CLK_SDMMC3 69
90 #define TEGRA124_CLK_PCIE 70
91 #define TEGRA124_CLK_OWR 71
92 #define TEGRA124_CLK_AFI 72
93 #define TEGRA124_CLK_CSITE 73
94 /* 74 */
95 /* 75 */
96 #define TEGRA124_CLK_LA 76
97 #define TEGRA124_CLK_TRACE 77
98 #define TEGRA124_CLK_SOC_THERM 78
99 #define TEGRA124_CLK_DTV 79
100 #define TEGRA124_CLK_NDSPEED 80
101 #define TEGRA124_CLK_I2CSLOW 81
102 #define TEGRA124_CLK_DSIB 82
103 #define TEGRA124_CLK_TSEC 83
104 /* 84 */
105 /* 85 */
106 /* 86 */
107 /* 87 */
108 /* 88 */
109 #define TEGRA124_CLK_XUSB_HOST 89
110 /* 90 */
111 #define TEGRA124_CLK_MSENC 91
112 #define TEGRA124_CLK_CSUS 92
113 /* 93 */
114 /* 94 */
115 /* 95 (bit affects xusb_dev and xusb_dev_src) */
116 
117 /* 96 */
118 /* 97 */
119 /* 98 */
120 #define TEGRA124_CLK_MSELECT 99
121 #define TEGRA124_CLK_TSENSOR 100
122 #define TEGRA124_CLK_I2S3 101
123 #define TEGRA124_CLK_I2S4 102
124 #define TEGRA124_CLK_I2C4 103
125 #define TEGRA124_CLK_SBC5 104
126 #define TEGRA124_CLK_SBC6 105
127 #define TEGRA124_CLK_D_AUDIO 106
128 #define TEGRA124_CLK_APBIF 107
129 #define TEGRA124_CLK_DAM0 108
130 #define TEGRA124_CLK_DAM1 109
131 #define TEGRA124_CLK_DAM2 110
132 #define TEGRA124_CLK_HDA2CODEC_2X 111
133 /* 112 */
134 #define TEGRA124_CLK_AUDIO0_2X 113
135 #define TEGRA124_CLK_AUDIO1_2X 114
136 #define TEGRA124_CLK_AUDIO2_2X 115
137 #define TEGRA124_CLK_AUDIO3_2X 116
138 #define TEGRA124_CLK_AUDIO4_2X 117
139 #define TEGRA124_CLK_SPDIF_2X 118
140 #define TEGRA124_CLK_ACTMON 119
141 #define TEGRA124_CLK_EXTERN1 120
142 #define TEGRA124_CLK_EXTERN2 121
143 #define TEGRA124_CLK_EXTERN3 122
144 #define TEGRA124_CLK_SATA_OOB 123
145 #define TEGRA124_CLK_SATA 124
146 #define TEGRA124_CLK_HDA 125
147 /* 126 */
148 #define TEGRA124_CLK_SE 127
149 
150 #define TEGRA124_CLK_HDA2HDMI 128
151 #define TEGRA124_CLK_SATA_COLD 129
152 /* 130 */
153 /* 131 */
154 /* 132 */
155 /* 133 */
156 /* 134 */
157 /* 135 */
158 /* 136 */
159 /* 137 */
160 /* 138 */
161 /* 139 */
162 /* 140 */
163 /* 141 */
164 /* 142 */
165 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
166 /*      xusb_host_src and xusb_ss_src) */
167 #define TEGRA124_CLK_CILAB 144
168 #define TEGRA124_CLK_CILCD 145
169 #define TEGRA124_CLK_CILE 146
170 #define TEGRA124_CLK_DSIALP 147
171 #define TEGRA124_CLK_DSIBLP 148
172 #define TEGRA124_CLK_ENTROPY 149
173 #define TEGRA124_CLK_DDS 150
174 /* 151 */
175 #define TEGRA124_CLK_DP2 152
176 #define TEGRA124_CLK_AMX 153
177 #define TEGRA124_CLK_ADX 154
178 /* 155 (bit affects dfll_ref and dfll_soc) */
179 #define TEGRA124_CLK_XUSB_SS 156
180 /* 157 */
181 /* 158 */
182 /* 159 */
183 
184 /* 160 */
185 /* 161 */
186 /* 162 */
187 /* 163 */
188 /* 164 */
189 /* 165 */
190 #define TEGRA124_CLK_I2C6 166
191 /* 167 */
192 /* 168 */
193 /* 169 */
194 /* 170 */
195 #define TEGRA124_CLK_VIM2_CLK 171
196 /* 172 */
197 /* 173 */
198 /* 174 */
199 /* 175 */
200 #define TEGRA124_CLK_HDMI_AUDIO 176
201 #define TEGRA124_CLK_CLK72MHZ 177
202 #define TEGRA124_CLK_VIC03 178
203 /* 179 */
204 #define TEGRA124_CLK_ADX1 180
205 #define TEGRA124_CLK_DPAUX 181
206 #define TEGRA124_CLK_SOR0 182
207 /* 183 */
208 #define TEGRA124_CLK_GPU 184
209 #define TEGRA124_CLK_AMX1 185
210 #define TEGRA124_CLK_AFC0 186
211 #define TEGRA124_CLK_AFC1 187
212 #define TEGRA124_CLK_AFC2 188
213 #define TEGRA124_CLK_AFC3 189
214 #define TEGRA124_CLK_AFC4 190
215 #define TEGRA124_CLK_AFC5 191
216 #define TEGRA124_CLK_UARTB 192
217 #define TEGRA124_CLK_VFIR 193
218 #define TEGRA124_CLK_SPDIF_IN 194
219 #define TEGRA124_CLK_SPDIF_OUT 195
220 #define TEGRA124_CLK_VI 196
221 #define TEGRA124_CLK_VI_SENSOR 197
222 #define TEGRA124_CLK_FUSE 198
223 #define TEGRA124_CLK_FUSE_BURN 199
224 #define TEGRA124_CLK_CLK_32K 200
225 #define TEGRA124_CLK_CLK_M 201
226 #define TEGRA124_CLK_CLK_M_DIV2 202
227 #define TEGRA124_CLK_CLK_M_DIV4 203
228 #define TEGRA124_CLK_PLL_REF 204
229 #define TEGRA124_CLK_PLL_C 205
230 #define TEGRA124_CLK_PLL_C_OUT1 206
231 #define TEGRA124_CLK_PLL_C2 207
232 #define TEGRA124_CLK_PLL_C3 208
233 #define TEGRA124_CLK_PLL_M 209
234 #define TEGRA124_CLK_PLL_M_OUT1 210
235 #define TEGRA124_CLK_PLL_P 211
236 #define TEGRA124_CLK_PLL_P_OUT1 212
237 #define TEGRA124_CLK_PLL_P_OUT2 213
238 #define TEGRA124_CLK_PLL_P_OUT3 214
239 #define TEGRA124_CLK_PLL_P_OUT4 215
240 #define TEGRA124_CLK_PLL_A 216
241 #define TEGRA124_CLK_PLL_A_OUT0 217
242 #define TEGRA124_CLK_PLL_D 218
243 #define TEGRA124_CLK_PLL_D_OUT0 219
244 #define TEGRA124_CLK_PLL_D2 220
245 #define TEGRA124_CLK_PLL_D2_OUT0 221
246 #define TEGRA124_CLK_PLL_U 222
247 #define TEGRA124_CLK_PLL_U_480M 223
248 
249 #define TEGRA124_CLK_PLL_U_60M 224
250 #define TEGRA124_CLK_PLL_U_48M 225
251 #define TEGRA124_CLK_PLL_U_12M 226
252 #define TEGRA124_CLK_PLL_X 227
253 #define TEGRA124_CLK_PLL_X_OUT0 228
254 #define TEGRA124_CLK_PLL_RE_VCO 229
255 #define TEGRA124_CLK_PLL_RE_OUT 230
256 #define TEGRA124_CLK_PLL_E 231
257 #define TEGRA124_CLK_SPDIF_IN_SYNC 232
258 #define TEGRA124_CLK_I2S0_SYNC 233
259 #define TEGRA124_CLK_I2S1_SYNC 234
260 #define TEGRA124_CLK_I2S2_SYNC 235
261 #define TEGRA124_CLK_I2S3_SYNC 236
262 #define TEGRA124_CLK_I2S4_SYNC 237
263 #define TEGRA124_CLK_VIMCLK_SYNC 238
264 #define TEGRA124_CLK_AUDIO0 239
265 #define TEGRA124_CLK_AUDIO1 240
266 #define TEGRA124_CLK_AUDIO2 241
267 #define TEGRA124_CLK_AUDIO3 242
268 #define TEGRA124_CLK_AUDIO4 243
269 #define TEGRA124_CLK_SPDIF 244
270 #define TEGRA124_CLK_CLK_OUT_1 245
271 #define TEGRA124_CLK_CLK_OUT_2 246
272 #define TEGRA124_CLK_CLK_OUT_3 247
273 #define TEGRA124_CLK_BLINK 248
274 /* 249 */
275 /* 250 */
276 /* 251 */
277 #define TEGRA124_CLK_XUSB_HOST_SRC 252
278 #define TEGRA124_CLK_XUSB_FALCON_SRC 253
279 #define TEGRA124_CLK_XUSB_FS_SRC 254
280 #define TEGRA124_CLK_XUSB_SS_SRC 255
281 
282 #define TEGRA124_CLK_XUSB_DEV_SRC 256
283 #define TEGRA124_CLK_XUSB_DEV 257
284 #define TEGRA124_CLK_XUSB_HS_SRC 258
285 #define TEGRA124_CLK_SCLK 259
286 #define TEGRA124_CLK_HCLK 260
287 #define TEGRA124_CLK_PCLK 261
288 #define TEGRA124_CLK_CCLK_G 262
289 #define TEGRA124_CLK_CCLK_LP 263
290 #define TEGRA124_CLK_DFLL_REF 264
291 #define TEGRA124_CLK_DFLL_SOC 265
292 #define TEGRA124_CLK_VI_SENSOR2 266
293 #define TEGRA124_CLK_PLL_P_OUT5 267
294 #define TEGRA124_CLK_CML0 268
295 #define TEGRA124_CLK_CML1 269
296 #define TEGRA124_CLK_PLL_C4 270
297 #define TEGRA124_CLK_PLL_DP 271
298 #define TEGRA124_CLK_PLL_E_MUX 272
299 /* 273 */
300 /* 274 */
301 /* 275 */
302 /* 276 */
303 /* 277 */
304 /* 278 */
305 /* 279 */
306 /* 280 */
307 /* 281 */
308 /* 282 */
309 /* 283 */
310 /* 284 */
311 /* 285 */
312 /* 286 */
313 /* 287 */
314 
315 /* 288 */
316 /* 289 */
317 /* 290 */
318 /* 291 */
319 /* 292 */
320 /* 293 */
321 /* 294 */
322 /* 295 */
323 /* 296 */
324 /* 297 */
325 /* 298 */
326 /* 299 */
327 #define TEGRA124_CLK_AUDIO0_MUX 300
328 #define TEGRA124_CLK_AUDIO1_MUX 301
329 #define TEGRA124_CLK_AUDIO2_MUX 302
330 #define TEGRA124_CLK_AUDIO3_MUX 303
331 #define TEGRA124_CLK_AUDIO4_MUX 304
332 #define TEGRA124_CLK_SPDIF_MUX 305
333 #define TEGRA124_CLK_CLK_OUT_1_MUX 306
334 #define TEGRA124_CLK_CLK_OUT_2_MUX 307
335 #define TEGRA124_CLK_CLK_OUT_3_MUX 308
336 #define TEGRA124_CLK_DSIA_MUX 309
337 #define TEGRA124_CLK_DSIB_MUX 310
338 #define TEGRA124_CLK_SOR0_LVDS 311
339 #define TEGRA124_CLK_PLL_M_UD 311
340 #define TEGRA124_CLK_CLK_MAX 312
341 
342 #endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
343