1 /*
2  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
5  */
6 
7 #ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
8 #define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
9 
10 /* PLL output is enable when x=1, with x=p,q or r */
11 #define PQR(p, q, r)	(((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
12 
13 /* st,clksrc: mandatory clock source */
14 
15 #define CLK_MPU_HSI		0x00000200
16 #define CLK_MPU_HSE		0x00000201
17 #define CLK_MPU_PLL1P		0x00000202
18 #define CLK_MPU_PLL1P_DIV	0x00000203
19 
20 #define CLK_AXI_HSI		0x00000240
21 #define CLK_AXI_HSE		0x00000241
22 #define CLK_AXI_PLL2P		0x00000242
23 
24 #define CLK_MCU_HSI		0x00000480
25 #define CLK_MCU_HSE		0x00000481
26 #define CLK_MCU_CSI		0x00000482
27 #define CLK_MCU_PLL3P		0x00000483
28 
29 #define CLK_PLL12_HSI		0x00000280
30 #define CLK_PLL12_HSE		0x00000281
31 
32 #define CLK_PLL3_HSI		0x00008200
33 #define CLK_PLL3_HSE		0x00008201
34 #define CLK_PLL3_CSI		0x00008202
35 
36 #define CLK_PLL4_HSI		0x00008240
37 #define CLK_PLL4_HSE		0x00008241
38 #define CLK_PLL4_CSI		0x00008242
39 #define CLK_PLL4_I2SCKIN	0x00008243
40 
41 #define CLK_RTC_DISABLED	0x00001400
42 #define CLK_RTC_LSE		0x00001401
43 #define CLK_RTC_LSI		0x00001402
44 #define CLK_RTC_HSE		0x00001403
45 
46 #define CLK_MCO1_HSI		0x00008000
47 #define CLK_MCO1_HSE		0x00008001
48 #define CLK_MCO1_CSI		0x00008002
49 #define CLK_MCO1_LSI		0x00008003
50 #define CLK_MCO1_LSE		0x00008004
51 #define CLK_MCO1_DISABLED	0x0000800F
52 
53 #define CLK_MCO2_MPU		0x00008040
54 #define CLK_MCO2_AXI		0x00008041
55 #define CLK_MCO2_MCU		0x00008042
56 #define CLK_MCO2_PLL4P		0x00008043
57 #define CLK_MCO2_HSE		0x00008044
58 #define CLK_MCO2_HSI		0x00008045
59 #define CLK_MCO2_DISABLED	0x0000804F
60 
61 /* st,pkcs: peripheral kernel clock source */
62 
63 #define CLK_I2C12_PCLK1		0x00008C00
64 #define CLK_I2C12_PLL4R		0x00008C01
65 #define CLK_I2C12_HSI		0x00008C02
66 #define CLK_I2C12_CSI		0x00008C03
67 #define CLK_I2C12_DISABLED	0x00008C07
68 
69 #define CLK_I2C35_PCLK1		0x00008C40
70 #define CLK_I2C35_PLL4R		0x00008C41
71 #define CLK_I2C35_HSI		0x00008C42
72 #define CLK_I2C35_CSI		0x00008C43
73 #define CLK_I2C35_DISABLED	0x00008C47
74 
75 #define CLK_I2C46_PCLK5		0x00000C00
76 #define CLK_I2C46_PLL3Q		0x00000C01
77 #define CLK_I2C46_HSI		0x00000C02
78 #define CLK_I2C46_CSI		0x00000C03
79 #define CLK_I2C46_DISABLED	0x00000C07
80 
81 #define CLK_SAI1_PLL4Q		0x00008C80
82 #define CLK_SAI1_PLL3Q		0x00008C81
83 #define CLK_SAI1_I2SCKIN	0x00008C82
84 #define CLK_SAI1_CKPER		0x00008C83
85 #define CLK_SAI1_PLL3R		0x00008C84
86 #define CLK_SAI1_DISABLED	0x00008C87
87 
88 #define CLK_SAI2_PLL4Q		0x00008CC0
89 #define CLK_SAI2_PLL3Q		0x00008CC1
90 #define CLK_SAI2_I2SCKIN	0x00008CC2
91 #define CLK_SAI2_CKPER		0x00008CC3
92 #define CLK_SAI2_SPDIF		0x00008CC4
93 #define CLK_SAI2_PLL3R		0x00008CC5
94 #define CLK_SAI2_DISABLED	0x00008CC7
95 
96 #define CLK_SAI3_PLL4Q		0x00008D00
97 #define CLK_SAI3_PLL3Q		0x00008D01
98 #define CLK_SAI3_I2SCKIN	0x00008D02
99 #define CLK_SAI3_CKPER		0x00008D03
100 #define CLK_SAI3_PLL3R		0x00008D04
101 #define CLK_SAI3_DISABLED	0x00008D07
102 
103 #define CLK_SAI4_PLL4Q		0x00008D40
104 #define CLK_SAI4_PLL3Q		0x00008D41
105 #define CLK_SAI4_I2SCKIN	0x00008D42
106 #define CLK_SAI4_CKPER		0x00008D43
107 #define CLK_SAI4_PLL3R		0x00008D44
108 #define CLK_SAI4_DISABLED	0x00008D47
109 
110 #define CLK_SPI2S1_PLL4P	0x00008D80
111 #define CLK_SPI2S1_PLL3Q	0x00008D81
112 #define CLK_SPI2S1_I2SCKIN	0x00008D82
113 #define CLK_SPI2S1_CKPER	0x00008D83
114 #define CLK_SPI2S1_PLL3R	0x00008D84
115 #define CLK_SPI2S1_DISABLED	0x00008D87
116 
117 #define CLK_SPI2S23_PLL4P	0x00008DC0
118 #define CLK_SPI2S23_PLL3Q	0x00008DC1
119 #define CLK_SPI2S23_I2SCKIN	0x00008DC2
120 #define CLK_SPI2S23_CKPER	0x00008DC3
121 #define CLK_SPI2S23_PLL3R	0x00008DC4
122 #define CLK_SPI2S23_DISABLED	0x00008DC7
123 
124 #define CLK_SPI45_PCLK2		0x00008E00
125 #define CLK_SPI45_PLL4Q		0x00008E01
126 #define CLK_SPI45_HSI		0x00008E02
127 #define CLK_SPI45_CSI		0x00008E03
128 #define CLK_SPI45_HSE		0x00008E04
129 #define CLK_SPI45_DISABLED	0x00008E07
130 
131 #define CLK_SPI6_PCLK5		0x00000C40
132 #define CLK_SPI6_PLL4Q		0x00000C41
133 #define CLK_SPI6_HSI		0x00000C42
134 #define CLK_SPI6_CSI		0x00000C43
135 #define CLK_SPI6_HSE		0x00000C44
136 #define CLK_SPI6_PLL3Q		0x00000C45
137 #define CLK_SPI6_DISABLED	0x00000C47
138 
139 #define CLK_UART6_PCLK2		0x00008E40
140 #define CLK_UART6_PLL4Q		0x00008E41
141 #define CLK_UART6_HSI		0x00008E42
142 #define CLK_UART6_CSI		0x00008E43
143 #define CLK_UART6_HSE		0x00008E44
144 #define CLK_UART6_DISABLED	0x00008E47
145 
146 #define CLK_UART24_PCLK1	0x00008E80
147 #define CLK_UART24_PLL4Q	0x00008E81
148 #define CLK_UART24_HSI		0x00008E82
149 #define CLK_UART24_CSI		0x00008E83
150 #define CLK_UART24_HSE		0x00008E84
151 #define CLK_UART24_DISABLED	0x00008E87
152 
153 #define CLK_UART35_PCLK1	0x00008EC0
154 #define CLK_UART35_PLL4Q	0x00008EC1
155 #define CLK_UART35_HSI		0x00008EC2
156 #define CLK_UART35_CSI		0x00008EC3
157 #define CLK_UART35_HSE		0x00008EC4
158 #define CLK_UART35_DISABLED	0x00008EC7
159 
160 #define CLK_UART78_PCLK1	0x00008F00
161 #define CLK_UART78_PLL4Q	0x00008F01
162 #define CLK_UART78_HSI		0x00008F02
163 #define CLK_UART78_CSI		0x00008F03
164 #define CLK_UART78_HSE		0x00008F04
165 #define CLK_UART78_DISABLED	0x00008F07
166 
167 #define CLK_UART1_PCLK5		0x00000C80
168 #define CLK_UART1_PLL3Q		0x00000C81
169 #define CLK_UART1_HSI		0x00000C82
170 #define CLK_UART1_CSI		0x00000C83
171 #define CLK_UART1_PLL4Q		0x00000C84
172 #define CLK_UART1_HSE		0x00000C85
173 #define CLK_UART1_DISABLED	0x00000C87
174 
175 #define CLK_SDMMC12_HCLK6	0x00008F40
176 #define CLK_SDMMC12_PLL3R	0x00008F41
177 #define CLK_SDMMC12_PLL4P	0x00008F42
178 #define CLK_SDMMC12_HSI		0x00008F43
179 #define CLK_SDMMC12_DISABLED	0x00008F47
180 
181 #define CLK_SDMMC3_HCLK2	0x00008F80
182 #define CLK_SDMMC3_PLL3R	0x00008F81
183 #define CLK_SDMMC3_PLL4P	0x00008F82
184 #define CLK_SDMMC3_HSI		0x00008F83
185 #define CLK_SDMMC3_DISABLED	0x00008F87
186 
187 #define CLK_ETH_PLL4P		0x00008FC0
188 #define CLK_ETH_PLL3Q		0x00008FC1
189 #define CLK_ETH_DISABLED	0x00008FC3
190 
191 #define CLK_QSPI_ACLK		0x00009000
192 #define CLK_QSPI_PLL3R		0x00009001
193 #define CLK_QSPI_PLL4P		0x00009002
194 #define CLK_QSPI_CKPER		0x00009003
195 
196 #define CLK_FMC_ACLK		0x00009040
197 #define CLK_FMC_PLL3R		0x00009041
198 #define CLK_FMC_PLL4P		0x00009042
199 #define CLK_FMC_CKPER		0x00009043
200 
201 #define CLK_FDCAN_HSE		0x000090C0
202 #define CLK_FDCAN_PLL3Q		0x000090C1
203 #define CLK_FDCAN_PLL4Q		0x000090C2
204 #define CLK_FDCAN_PLL4R		0x000090C3
205 
206 #define CLK_SPDIF_PLL4P		0x00009140
207 #define CLK_SPDIF_PLL3Q		0x00009141
208 #define CLK_SPDIF_HSI		0x00009142
209 #define CLK_SPDIF_DISABLED	0x00009143
210 
211 #define CLK_CEC_LSE		0x00009180
212 #define CLK_CEC_LSI		0x00009181
213 #define CLK_CEC_CSI_DIV122	0x00009182
214 #define CLK_CEC_DISABLED	0x00009183
215 
216 #define CLK_USBPHY_HSE		0x000091C0
217 #define CLK_USBPHY_PLL4R	0x000091C1
218 #define CLK_USBPHY_HSE_DIV2	0x000091C2
219 #define CLK_USBPHY_DISABLED	0x000091C3
220 
221 #define CLK_USBO_PLL4R		0x800091C0
222 #define CLK_USBO_USBPHY		0x800091C1
223 
224 #define CLK_RNG1_CSI		0x00000CC0
225 #define CLK_RNG1_PLL4R		0x00000CC1
226 #define CLK_RNG1_LSE		0x00000CC2
227 #define CLK_RNG1_LSI		0x00000CC3
228 
229 #define CLK_RNG2_CSI		0x00009200
230 #define CLK_RNG2_PLL4R		0x00009201
231 #define CLK_RNG2_LSE		0x00009202
232 #define CLK_RNG2_LSI		0x00009203
233 
234 #define CLK_CKPER_HSI		0x00000D00
235 #define CLK_CKPER_CSI		0x00000D01
236 #define CLK_CKPER_HSE		0x00000D02
237 #define CLK_CKPER_DISABLED	0x00000D03
238 
239 #define CLK_STGEN_HSI		0x00000D40
240 #define CLK_STGEN_HSE		0x00000D41
241 #define CLK_STGEN_DISABLED	0x00000D43
242 
243 #define CLK_DSI_DSIPLL		0x00009240
244 #define CLK_DSI_PLL4P		0x00009241
245 
246 #define CLK_ADC_PLL4R		0x00009280
247 #define CLK_ADC_CKPER		0x00009281
248 #define CLK_ADC_PLL3Q		0x00009282
249 #define CLK_ADC_DISABLED	0x00009283
250 
251 #define CLK_LPTIM45_PCLK3	0x000092C0
252 #define CLK_LPTIM45_PLL4P	0x000092C1
253 #define CLK_LPTIM45_PLL3Q	0x000092C2
254 #define CLK_LPTIM45_LSE		0x000092C3
255 #define CLK_LPTIM45_LSI		0x000092C4
256 #define CLK_LPTIM45_CKPER	0x000092C5
257 #define CLK_LPTIM45_DISABLED	0x000092C7
258 
259 #define CLK_LPTIM23_PCLK3	0x00009300
260 #define CLK_LPTIM23_PLL4Q	0x00009301
261 #define CLK_LPTIM23_CKPER	0x00009302
262 #define CLK_LPTIM23_LSE		0x00009303
263 #define CLK_LPTIM23_LSI		0x00009304
264 #define CLK_LPTIM23_DISABLED	0x00009307
265 
266 #define CLK_LPTIM1_PCLK1	0x00009340
267 #define CLK_LPTIM1_PLL4P	0x00009341
268 #define CLK_LPTIM1_PLL3Q	0x00009342
269 #define CLK_LPTIM1_LSE		0x00009343
270 #define CLK_LPTIM1_LSI		0x00009344
271 #define CLK_LPTIM1_CKPER	0x00009345
272 #define CLK_LPTIM1_DISABLED	0x00009347
273 
274 /* define for st,pll /csg */
275 #define SSCG_MODE_CENTER_SPREAD	0
276 #define SSCG_MODE_DOWN_SPREAD	1
277 
278 /* define for st,drive */
279 #define LSEDRV_LOWEST		0
280 #define LSEDRV_MEDIUM_LOW	1
281 #define LSEDRV_MEDIUM_HIGH	2
282 #define LSEDRV_HIGHEST		3
283 
284 #endif
285