1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 4 * Author: Shawn Lin <shawn.lin@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 9 10 /* pll id */ 11 #define PLL_APLL 0 12 #define PLL_DPLL 1 13 #define PLL_GPLL 2 14 #define ARMCLK 3 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_SPI0 65 18 #define SCLK_NANDC 67 19 #define SCLK_SDMMC 68 20 #define SCLK_SDIO 69 21 #define SCLK_EMMC 71 22 #define SCLK_UART0 72 23 #define SCLK_UART1 73 24 #define SCLK_UART2 74 25 #define SCLK_I2S0 75 26 #define SCLK_I2S1 76 27 #define SCLK_I2S2 77 28 #define SCLK_TIMER0 78 29 #define SCLK_TIMER1 79 30 #define SCLK_SFC 80 31 #define SCLK_SDMMC_DRV 81 32 #define SCLK_SDIO_DRV 82 33 #define SCLK_EMMC_DRV 83 34 #define SCLK_SDMMC_SAMPLE 84 35 #define SCLK_SDIO_SAMPLE 85 36 #define SCLK_EMMC_SAMPLE 86 37 #define SCLK_VENC_CORE 87 38 #define SCLK_HEVC_CORE 88 39 #define SCLK_HEVC_CABAC 89 40 #define SCLK_PWM0_PMU 90 41 #define SCLK_I2C0_PMU 91 42 #define SCLK_WIFI 92 43 #define SCLK_CIFOUT 93 44 #define SCLK_MIPI_CSI_OUT 94 45 #define SCLK_CIF0 95 46 #define SCLK_CIF1 96 47 #define SCLK_CIF2 97 48 #define SCLK_CIF3 98 49 #define SCLK_DSP 99 50 #define SCLK_DSP_IOP 100 51 #define SCLK_DSP_EPP 101 52 #define SCLK_DSP_EDP 102 53 #define SCLK_DSP_EDAP 103 54 #define SCLK_CVBS_HOST 104 55 #define SCLK_HDMI_SFR 105 56 #define SCLK_HDMI_CEC 106 57 #define SCLK_CRYPTO 107 58 #define SCLK_SPI 108 59 #define SCLK_SARADC 109 60 #define SCLK_TSADC 110 61 #define SCLK_MAC_PRE 111 62 #define SCLK_MAC 112 63 #define SCLK_MAC_RX 113 64 #define SCLK_MAC_REF 114 65 #define SCLK_MAC_REFOUT 115 66 #define SCLK_DSP_PFM 116 67 #define SCLK_RGA 117 68 #define SCLK_I2C1 118 69 #define SCLK_I2C2 119 70 #define SCLK_I2C3 120 71 #define SCLK_PWM 121 72 #define SCLK_ISP 122 73 #define SCLK_USBPHY 123 74 #define SCLK_I2S0_SRC 124 75 #define SCLK_I2S1_SRC 125 76 #define SCLK_I2S2_SRC 126 77 #define SCLK_UART0_SRC 127 78 #define SCLK_UART1_SRC 128 79 #define SCLK_UART2_SRC 129 80 #define SCLK_MAC_TX 130 81 #define SCLK_MACREF 131 82 #define SCLK_MACREF_OUT 132 83 84 #define DCLK_VOP_SRC 185 85 #define DCLK_HDMIPHY 186 86 #define DCLK_VOP 187 87 88 /* aclk gates */ 89 #define ACLK_DMAC 192 90 #define ACLK_PRE 193 91 #define ACLK_CORE 194 92 #define ACLK_ENMCORE 195 93 #define ACLK_RKVENC 196 94 #define ACLK_RKVDEC 197 95 #define ACLK_VPU 198 96 #define ACLK_CIF0 199 97 #define ACLK_VIO0 200 98 #define ACLK_VIO1 201 99 #define ACLK_VOP 202 100 #define ACLK_IEP 203 101 #define ACLK_RGA 204 102 #define ACLK_ISP 205 103 #define ACLK_CIF1 206 104 #define ACLK_CIF2 207 105 #define ACLK_CIF3 208 106 #define ACLK_PERI 209 107 #define ACLK_GMAC 210 108 109 /* pclk gates */ 110 #define PCLK_GPIO1 256 111 #define PCLK_GPIO2 257 112 #define PCLK_GPIO3 258 113 #define PCLK_GRF 259 114 #define PCLK_I2C1 260 115 #define PCLK_I2C2 261 116 #define PCLK_I2C3 262 117 #define PCLK_SPI 263 118 #define PCLK_SFC 264 119 #define PCLK_UART0 265 120 #define PCLK_UART1 266 121 #define PCLK_UART2 267 122 #define PCLK_TSADC 268 123 #define PCLK_PWM 269 124 #define PCLK_TIMER 270 125 #define PCLK_PERI 271 126 #define PCLK_GPIO0_PMU 272 127 #define PCLK_I2C0_PMU 273 128 #define PCLK_PWM0_PMU 274 129 #define PCLK_ISP 275 130 #define PCLK_VIO 276 131 #define PCLK_MIPI_DSI 277 132 #define PCLK_HDMI_CTRL 278 133 #define PCLK_SARADC 279 134 #define PCLK_DSP_CFG 280 135 #define PCLK_BUS 281 136 #define PCLK_EFUSE0 282 137 #define PCLK_EFUSE1 283 138 #define PCLK_WDT 284 139 #define PCLK_GMAC 285 140 141 /* hclk gates */ 142 #define HCLK_I2S0_8CH 320 143 #define HCLK_I2S1_2CH 321 144 #define HCLK_I2S2_2CH 322 145 #define HCLK_NANDC 323 146 #define HCLK_SDMMC 324 147 #define HCLK_SDIO 325 148 #define HCLK_EMMC 326 149 #define HCLK_PERI 327 150 #define HCLK_SFC 328 151 #define HCLK_RKVENC 329 152 #define HCLK_RKVDEC 330 153 #define HCLK_CIF0 331 154 #define HCLK_VIO 332 155 #define HCLK_VOP 333 156 #define HCLK_IEP 334 157 #define HCLK_RGA 335 158 #define HCLK_ISP 336 159 #define HCLK_CRYPTO_MST 337 160 #define HCLK_CRYPTO_SLV 338 161 #define HCLK_HOST0 339 162 #define HCLK_OTG 340 163 #define HCLK_CIF1 341 164 #define HCLK_CIF2 342 165 #define HCLK_CIF3 343 166 #define HCLK_BUS 344 167 #define HCLK_VPU 345 168 169 #define CLK_NR_CLKS (HCLK_VPU + 1) 170 171 /* reset id */ 172 #define SRST_CORE_PO_AD 0 173 #define SRST_CORE_AD 1 174 #define SRST_L2_AD 2 175 #define SRST_CPU_NIU_AD 3 176 #define SRST_CORE_PO 4 177 #define SRST_CORE 5 178 #define SRST_L2 6 179 #define SRST_CORE_DBG 8 180 #define PRST_DBG 9 181 #define RST_DAP 10 182 #define PRST_DBG_NIU 11 183 #define ARST_STRC_SYS_AD 15 184 185 #define SRST_DDRPHY_CLKDIV 16 186 #define SRST_DDRPHY 17 187 #define PRST_DDRPHY 18 188 #define PRST_HDMIPHY 19 189 #define PRST_VDACPHY 20 190 #define PRST_VADCPHY 21 191 #define PRST_MIPI_CSI_PHY 22 192 #define PRST_MIPI_DSI_PHY 23 193 #define PRST_ACODEC 24 194 #define ARST_BUS_NIU 25 195 #define PRST_TOP_NIU 26 196 #define ARST_INTMEM 27 197 #define HRST_ROM 28 198 #define ARST_DMAC 29 199 #define SRST_MSCH_NIU 30 200 #define PRST_MSCH_NIU 31 201 202 #define PRST_DDRUPCTL 32 203 #define NRST_DDRUPCTL 33 204 #define PRST_DDRMON 34 205 #define HRST_I2S0_8CH 35 206 #define MRST_I2S0_8CH 36 207 #define HRST_I2S1_2CH 37 208 #define MRST_IS21_2CH 38 209 #define HRST_I2S2_2CH 39 210 #define MRST_I2S2_2CH 40 211 #define HRST_CRYPTO 41 212 #define SRST_CRYPTO 42 213 #define PRST_SPI 43 214 #define SRST_SPI 44 215 #define PRST_UART0 45 216 #define PRST_UART1 46 217 #define PRST_UART2 47 218 219 #define SRST_UART0 48 220 #define SRST_UART1 49 221 #define SRST_UART2 50 222 #define PRST_I2C1 51 223 #define PRST_I2C2 52 224 #define PRST_I2C3 53 225 #define SRST_I2C1 54 226 #define SRST_I2C2 55 227 #define SRST_I2C3 56 228 #define PRST_PWM1 58 229 #define SRST_PWM1 60 230 #define PRST_WDT 61 231 #define PRST_GPIO1 62 232 #define PRST_GPIO2 63 233 234 #define PRST_GPIO3 64 235 #define PRST_GRF 65 236 #define PRST_EFUSE 66 237 #define PRST_EFUSE512 67 238 #define PRST_TIMER0 68 239 #define SRST_TIMER0 69 240 #define SRST_TIMER1 70 241 #define PRST_TSADC 71 242 #define SRST_TSADC 72 243 #define PRST_SARADC 73 244 #define SRST_SARADC 74 245 #define HRST_SYSBUS 75 246 #define PRST_USBGRF 76 247 248 #define ARST_PERIPH_NIU 80 249 #define HRST_PERIPH_NIU 81 250 #define PRST_PERIPH_NIU 82 251 #define HRST_PERIPH 83 252 #define HRST_SDMMC 84 253 #define HRST_SDIO 85 254 #define HRST_EMMC 86 255 #define HRST_NANDC 87 256 #define NRST_NANDC 88 257 #define HRST_SFC 89 258 #define SRST_SFC 90 259 #define ARST_GMAC 91 260 #define HRST_OTG 92 261 #define SRST_OTG 93 262 #define SRST_OTG_ADP 94 263 #define HRST_HOST0 95 264 265 #define HRST_HOST0_AUX 96 266 #define HRST_HOST0_ARB 97 267 #define SRST_HOST0_EHCIPHY 98 268 #define SRST_HOST0_UTMI 99 269 #define SRST_USBPOR 100 270 #define SRST_UTMI0 101 271 #define SRST_UTMI1 102 272 273 #define ARST_VIO0_NIU 102 274 #define ARST_VIO1_NIU 103 275 #define HRST_VIO_NIU 104 276 #define PRST_VIO_NIU 105 277 #define ARST_VOP 106 278 #define HRST_VOP 107 279 #define DRST_VOP 108 280 #define ARST_IEP 109 281 #define HRST_IEP 110 282 #define ARST_RGA 111 283 #define HRST_RGA 112 284 #define SRST_RGA 113 285 #define PRST_CVBS 114 286 #define PRST_HDMI 115 287 #define SRST_HDMI 116 288 #define PRST_MIPI_DSI 117 289 290 #define ARST_ISP_NIU 118 291 #define HRST_ISP_NIU 119 292 #define HRST_ISP 120 293 #define SRST_ISP 121 294 #define ARST_VIP0 122 295 #define HRST_VIP0 123 296 #define PRST_VIP0 124 297 #define ARST_VIP1 125 298 #define HRST_VIP1 126 299 #define PRST_VIP1 127 300 #define ARST_VIP2 128 301 #define HRST_VIP2 129 302 #define PRST_VIP2 120 303 #define ARST_VIP3 121 304 #define HRST_VIP3 122 305 #define PRST_VIP4 123 306 307 #define PRST_CIF1TO4 124 308 #define SRST_CVBS_CLK 125 309 #define HRST_CVBS 126 310 311 #define ARST_VPU_NIU 140 312 #define HRST_VPU_NIU 141 313 #define ARST_VPU 142 314 #define HRST_VPU 143 315 #define ARST_RKVDEC_NIU 144 316 #define HRST_RKVDEC_NIU 145 317 #define ARST_RKVDEC 146 318 #define HRST_RKVDEC 147 319 #define SRST_RKVDEC_CABAC 148 320 #define SRST_RKVDEC_CORE 149 321 #define ARST_RKVENC_NIU 150 322 #define HRST_RKVENC_NIU 151 323 #define ARST_RKVENC 152 324 #define HRST_RKVENC 153 325 #define SRST_RKVENC_CORE 154 326 327 #define SRST_DSP_CORE 156 328 #define SRST_DSP_SYS 157 329 #define SRST_DSP_GLOBAL 158 330 #define SRST_DSP_OECM 159 331 #define PRST_DSP_IOP_NIU 160 332 #define ARST_DSP_EPP_NIU 161 333 #define ARST_DSP_EDP_NIU 162 334 #define PRST_DSP_DBG_NIU 163 335 #define PRST_DSP_CFG_NIU 164 336 #define PRST_DSP_GRF 165 337 #define PRST_DSP_MAILBOX 166 338 #define PRST_DSP_INTC 167 339 #define PRST_DSP_PFM_MON 169 340 #define SRST_DSP_PFM_MON 170 341 #define ARST_DSP_EDAP_NIU 171 342 343 #define SRST_PMU 172 344 #define SRST_PMU_I2C0 173 345 #define PRST_PMU_I2C0 174 346 #define PRST_PMU_GPIO0 175 347 #define PRST_PMU_INTMEM 176 348 #define PRST_PMU_PWM0 177 349 #define SRST_PMU_PWM0 178 350 #define PRST_PMU_GRF 179 351 #define SRST_PMU_NIU 180 352 #define SRST_PMU_PVTM 181 353 #define ARST_DSP_EDP_PERF 184 354 #define ARST_DSP_EPP_PERF 185 355 356 #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 357