1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H 9 10 /* core clocks */ 11 #define PLL_APLLL 1 12 #define PLL_APLLB 2 13 #define PLL_DPLL 3 14 #define PLL_CPLL 4 15 #define PLL_GPLL 5 16 #define PLL_NPLL 6 17 #define PLL_VPLL 7 18 #define ARMCLKL 8 19 #define ARMCLKB 9 20 21 /* sclk gates (special clocks) */ 22 #define SCLK_I2C1 65 23 #define SCLK_I2C2 66 24 #define SCLK_I2C3 67 25 #define SCLK_I2C5 68 26 #define SCLK_I2C6 69 27 #define SCLK_I2C7 70 28 #define SCLK_SPI0 71 29 #define SCLK_SPI1 72 30 #define SCLK_SPI2 73 31 #define SCLK_SPI4 74 32 #define SCLK_SPI5 75 33 #define SCLK_SDMMC 76 34 #define SCLK_SDIO 77 35 #define SCLK_EMMC 78 36 #define SCLK_TSADC 79 37 #define SCLK_SARADC 80 38 #define SCLK_UART0 81 39 #define SCLK_UART1 82 40 #define SCLK_UART2 83 41 #define SCLK_UART3 84 42 #define SCLK_SPDIF_8CH 85 43 #define SCLK_I2S0_8CH 86 44 #define SCLK_I2S1_8CH 87 45 #define SCLK_I2S2_8CH 88 46 #define SCLK_I2S_8CH_OUT 89 47 #define SCLK_TIMER00 90 48 #define SCLK_TIMER01 91 49 #define SCLK_TIMER02 92 50 #define SCLK_TIMER03 93 51 #define SCLK_TIMER04 94 52 #define SCLK_TIMER05 95 53 #define SCLK_TIMER06 96 54 #define SCLK_TIMER07 97 55 #define SCLK_TIMER08 98 56 #define SCLK_TIMER09 99 57 #define SCLK_TIMER10 100 58 #define SCLK_TIMER11 101 59 #define SCLK_MACREF 102 60 #define SCLK_MAC_RX 103 61 #define SCLK_MAC_TX 104 62 #define SCLK_MAC 105 63 #define SCLK_MACREF_OUT 106 64 #define SCLK_VOP0_PWM 107 65 #define SCLK_VOP1_PWM 108 66 #define SCLK_RGA_CORE 109 67 #define SCLK_ISP0 110 68 #define SCLK_ISP1 111 69 #define SCLK_HDMI_CEC 112 70 #define SCLK_HDMI_SFR 113 71 #define SCLK_DP_CORE 114 72 #define SCLK_PVTM_CORE_L 115 73 #define SCLK_PVTM_CORE_B 116 74 #define SCLK_PVTM_GPU 117 75 #define SCLK_PVTM_DDR 118 76 #define SCLK_MIPIDPHY_REF 119 77 #define SCLK_MIPIDPHY_CFG 120 78 #define SCLK_HSICPHY 121 79 #define SCLK_USBPHY480M 122 80 #define SCLK_USB2PHY0_REF 123 81 #define SCLK_USB2PHY1_REF 124 82 #define SCLK_UPHY0_TCPDPHY_REF 125 83 #define SCLK_UPHY0_TCPDCORE 126 84 #define SCLK_UPHY1_TCPDPHY_REF 127 85 #define SCLK_UPHY1_TCPDCORE 128 86 #define SCLK_USB3OTG0_REF 129 87 #define SCLK_USB3OTG1_REF 130 88 #define SCLK_USB3OTG0_SUSPEND 131 89 #define SCLK_USB3OTG1_SUSPEND 132 90 #define SCLK_CRYPTO0 133 91 #define SCLK_CRYPTO1 134 92 #define SCLK_CCI_TRACE 135 93 #define SCLK_CS 136 94 #define SCLK_CIF_OUT 137 95 #define SCLK_PCIEPHY_REF 138 96 #define SCLK_PCIE_CORE 139 97 #define SCLK_M0_PERILP 140 98 #define SCLK_M0_PERILP_DEC 141 99 #define SCLK_CM0S 142 100 #define SCLK_DBG_NOC 143 101 #define SCLK_DBG_PD_CORE_B 144 102 #define SCLK_DBG_PD_CORE_L 145 103 #define SCLK_DFIMON0_TIMER 146 104 #define SCLK_DFIMON1_TIMER 147 105 #define SCLK_INTMEM0 148 106 #define SCLK_INTMEM1 149 107 #define SCLK_INTMEM2 150 108 #define SCLK_INTMEM3 151 109 #define SCLK_INTMEM4 152 110 #define SCLK_INTMEM5 153 111 #define SCLK_SDMMC_DRV 154 112 #define SCLK_SDMMC_SAMPLE 155 113 #define SCLK_SDIO_DRV 156 114 #define SCLK_SDIO_SAMPLE 157 115 #define SCLK_VDU_CORE 158 116 #define SCLK_VDU_CA 159 117 #define SCLK_PCIE_PM 160 118 #define SCLK_SPDIF_REC_DPTX 161 119 #define SCLK_DPHY_PLL 162 120 #define SCLK_DPHY_TX0_CFG 163 121 #define SCLK_DPHY_TX1RX1_CFG 164 122 #define SCLK_DPHY_RX0_CFG 165 123 #define SCLK_RMII_SRC 166 124 #define SCLK_PCIEPHY_REF100M 167 125 126 #define DCLK_VOP0 180 127 #define DCLK_VOP1 181 128 #define DCLK_VOP0_DIV 182 129 #define DCLK_VOP1_DIV 183 130 #define DCLK_M0_PERILP 184 131 132 #define FCLK_CM0S 190 133 134 /* aclk gates */ 135 #define ACLK_PERIHP 192 136 #define ACLK_PERIHP_NOC 193 137 #define ACLK_PERILP0 194 138 #define ACLK_PERILP0_NOC 195 139 #define ACLK_PERF_PCIE 196 140 #define ACLK_PCIE 197 141 #define ACLK_INTMEM 198 142 #define ACLK_TZMA 199 143 #define ACLK_DCF 200 144 #define ACLK_CCI 201 145 #define ACLK_CCI_NOC0 202 146 #define ACLK_CCI_NOC1 203 147 #define ACLK_CCI_GRF 204 148 #define ACLK_CENTER 205 149 #define ACLK_CENTER_MAIN_NOC 206 150 #define ACLK_CENTER_PERI_NOC 207 151 #define ACLK_GPU 208 152 #define ACLK_PERF_GPU 209 153 #define ACLK_GPU_GRF 210 154 #define ACLK_DMAC0_PERILP 211 155 #define ACLK_DMAC1_PERILP 212 156 #define ACLK_GMAC 213 157 #define ACLK_GMAC_NOC 214 158 #define ACLK_PERF_GMAC 215 159 #define ACLK_VOP0_NOC 216 160 #define ACLK_VOP0 217 161 #define ACLK_VOP1_NOC 218 162 #define ACLK_VOP1 219 163 #define ACLK_RGA 220 164 #define ACLK_RGA_NOC 221 165 #define ACLK_HDCP 222 166 #define ACLK_HDCP_NOC 223 167 #define ACLK_HDCP22 224 168 #define ACLK_IEP 225 169 #define ACLK_IEP_NOC 226 170 #define ACLK_VIO 227 171 #define ACLK_VIO_NOC 228 172 #define ACLK_ISP0 229 173 #define ACLK_ISP1 230 174 #define ACLK_ISP0_NOC 231 175 #define ACLK_ISP1_NOC 232 176 #define ACLK_ISP0_WRAPPER 233 177 #define ACLK_ISP1_WRAPPER 234 178 #define ACLK_VCODEC 235 179 #define ACLK_VCODEC_NOC 236 180 #define ACLK_VDU 237 181 #define ACLK_VDU_NOC 238 182 #define ACLK_PERI 239 183 #define ACLK_EMMC 240 184 #define ACLK_EMMC_CORE 241 185 #define ACLK_EMMC_NOC 242 186 #define ACLK_EMMC_GRF 243 187 #define ACLK_USB3 244 188 #define ACLK_USB3_NOC 245 189 #define ACLK_USB3OTG0 246 190 #define ACLK_USB3OTG1 247 191 #define ACLK_USB3_RKSOC_AXI_PERF 248 192 #define ACLK_USB3_GRF 249 193 #define ACLK_GIC 250 194 #define ACLK_GIC_NOC 251 195 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252 196 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253 197 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254 198 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255 199 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 200 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 201 #define ACLK_ADB400M_PD_CORE_L 258 202 #define ACLK_ADB400M_PD_CORE_B 259 203 #define ACLK_PERF_CORE_L 260 204 #define ACLK_PERF_CORE_B 261 205 #define ACLK_GIC_PRE 262 206 #define ACLK_VOP0_PRE 263 207 #define ACLK_VOP1_PRE 264 208 209 /* pclk gates */ 210 #define PCLK_PERIHP 320 211 #define PCLK_PERIHP_NOC 321 212 #define PCLK_PERILP0 322 213 #define PCLK_PERILP1 323 214 #define PCLK_PERILP1_NOC 324 215 #define PCLK_PERILP_SGRF 325 216 #define PCLK_PERIHP_GRF 326 217 #define PCLK_PCIE 327 218 #define PCLK_SGRF 328 219 #define PCLK_INTR_ARB 329 220 #define PCLK_CENTER_MAIN_NOC 330 221 #define PCLK_CIC 331 222 #define PCLK_COREDBG_B 332 223 #define PCLK_COREDBG_L 333 224 #define PCLK_DBG_CXCS_PD_CORE_B 334 225 #define PCLK_DCF 335 226 #define PCLK_GPIO2 336 227 #define PCLK_GPIO3 337 228 #define PCLK_GPIO4 338 229 #define PCLK_GRF 339 230 #define PCLK_HSICPHY 340 231 #define PCLK_I2C1 341 232 #define PCLK_I2C2 342 233 #define PCLK_I2C3 343 234 #define PCLK_I2C5 344 235 #define PCLK_I2C6 345 236 #define PCLK_I2C7 346 237 #define PCLK_SPI0 347 238 #define PCLK_SPI1 348 239 #define PCLK_SPI2 349 240 #define PCLK_SPI4 350 241 #define PCLK_SPI5 351 242 #define PCLK_UART0 352 243 #define PCLK_UART1 353 244 #define PCLK_UART2 354 245 #define PCLK_UART3 355 246 #define PCLK_TSADC 356 247 #define PCLK_SARADC 357 248 #define PCLK_GMAC 358 249 #define PCLK_GMAC_NOC 359 250 #define PCLK_TIMER0 360 251 #define PCLK_TIMER1 361 252 #define PCLK_EDP 362 253 #define PCLK_EDP_NOC 363 254 #define PCLK_EDP_CTRL 364 255 #define PCLK_VIO 365 256 #define PCLK_VIO_NOC 366 257 #define PCLK_VIO_GRF 367 258 #define PCLK_MIPI_DSI0 368 259 #define PCLK_MIPI_DSI1 369 260 #define PCLK_HDCP 370 261 #define PCLK_HDCP_NOC 371 262 #define PCLK_HDMI_CTRL 372 263 #define PCLK_DP_CTRL 373 264 #define PCLK_HDCP22 374 265 #define PCLK_GASKET 375 266 #define PCLK_DDR 376 267 #define PCLK_DDR_MON 377 268 #define PCLK_DDR_SGRF 378 269 #define PCLK_ISP1_WRAPPER 379 270 #define PCLK_WDT 380 271 #define PCLK_EFUSE1024NS 381 272 #define PCLK_EFUSE1024S 382 273 #define PCLK_PMU_INTR_ARB 383 274 #define PCLK_MAILBOX0 384 275 #define PCLK_USBPHY_MUX_G 385 276 #define PCLK_UPHY0_TCPHY_G 386 277 #define PCLK_UPHY0_TCPD_G 387 278 #define PCLK_UPHY1_TCPHY_G 388 279 #define PCLK_UPHY1_TCPD_G 389 280 #define PCLK_ALIVE 390 281 282 /* hclk gates */ 283 #define HCLK_PERIHP 448 284 #define HCLK_PERILP0 449 285 #define HCLK_PERILP1 450 286 #define HCLK_PERILP0_NOC 451 287 #define HCLK_PERILP1_NOC 452 288 #define HCLK_M0_PERILP 453 289 #define HCLK_M0_PERILP_NOC 454 290 #define HCLK_AHB1TOM 455 291 #define HCLK_HOST0 456 292 #define HCLK_HOST0_ARB 457 293 #define HCLK_HOST1 458 294 #define HCLK_HOST1_ARB 459 295 #define HCLK_HSIC 460 296 #define HCLK_SD 461 297 #define HCLK_SDMMC 462 298 #define HCLK_SDMMC_NOC 463 299 #define HCLK_M_CRYPTO0 464 300 #define HCLK_M_CRYPTO1 465 301 #define HCLK_S_CRYPTO0 466 302 #define HCLK_S_CRYPTO1 467 303 #define HCLK_I2S0_8CH 468 304 #define HCLK_I2S1_8CH 469 305 #define HCLK_I2S2_8CH 470 306 #define HCLK_SPDIF 471 307 #define HCLK_VOP0_NOC 472 308 #define HCLK_VOP0 473 309 #define HCLK_VOP1_NOC 474 310 #define HCLK_VOP1 475 311 #define HCLK_ROM 476 312 #define HCLK_IEP 477 313 #define HCLK_IEP_NOC 478 314 #define HCLK_ISP0 479 315 #define HCLK_ISP1 480 316 #define HCLK_ISP0_NOC 481 317 #define HCLK_ISP1_NOC 482 318 #define HCLK_ISP0_WRAPPER 483 319 #define HCLK_ISP1_WRAPPER 484 320 #define HCLK_RGA 485 321 #define HCLK_RGA_NOC 486 322 #define HCLK_HDCP 487 323 #define HCLK_HDCP_NOC 488 324 #define HCLK_HDCP22 489 325 #define HCLK_VCODEC 490 326 #define HCLK_VCODEC_NOC 491 327 #define HCLK_VDU 492 328 #define HCLK_VDU_NOC 493 329 #define HCLK_SDIO 494 330 #define HCLK_SDIO_NOC 495 331 #define HCLK_SDIOAUDIO_NOC 496 332 333 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) 334 335 /* pmu-clocks indices */ 336 337 #define PLL_PPLL 1 338 339 #define SCLK_32K_SUSPEND_PMU 2 340 #define SCLK_SPI3_PMU 3 341 #define SCLK_TIMER12_PMU 4 342 #define SCLK_TIMER13_PMU 5 343 #define SCLK_UART4_PMU 6 344 #define SCLK_PVTM_PMU 7 345 #define SCLK_WIFI_PMU 8 346 #define SCLK_I2C0_PMU 9 347 #define SCLK_I2C4_PMU 10 348 #define SCLK_I2C8_PMU 11 349 350 #define PCLK_SRC_PMU 19 351 #define PCLK_PMU 20 352 #define PCLK_PMUGRF_PMU 21 353 #define PCLK_INTMEM1_PMU 22 354 #define PCLK_GPIO0_PMU 23 355 #define PCLK_GPIO1_PMU 24 356 #define PCLK_SGRF_PMU 25 357 #define PCLK_NOC_PMU 26 358 #define PCLK_I2C0_PMU 27 359 #define PCLK_I2C4_PMU 28 360 #define PCLK_I2C8_PMU 29 361 #define PCLK_RKPWM_PMU 30 362 #define PCLK_SPI3_PMU 31 363 #define PCLK_TIMER_PMU 32 364 #define PCLK_MAILBOX_PMU 33 365 #define PCLK_UART4_PMU 34 366 #define PCLK_WDT_M0_PMU 35 367 368 #define FCLK_CM0S_SRC_PMU 44 369 #define FCLK_CM0S_PMU 45 370 #define SCLK_CM0S_PMU 46 371 #define HCLK_CM0S_PMU 47 372 #define DCLK_CM0S_PMU 48 373 #define PCLK_INTR_ARB_PMU 49 374 #define HCLK_NOC_PMU 50 375 376 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) 377 378 /* soft-reset indices */ 379 380 /* cru_softrst_con0 */ 381 #define SRST_CORE_L0 0 382 #define SRST_CORE_B0 1 383 #define SRST_CORE_PO_L0 2 384 #define SRST_CORE_PO_B0 3 385 #define SRST_L2_L 4 386 #define SRST_L2_B 5 387 #define SRST_ADB_L 6 388 #define SRST_ADB_B 7 389 #define SRST_A_CCI 8 390 #define SRST_A_CCIM0_NOC 9 391 #define SRST_A_CCIM1_NOC 10 392 #define SRST_DBG_NOC 11 393 394 /* cru_softrst_con1 */ 395 #define SRST_CORE_L0_T 16 396 #define SRST_CORE_L1 17 397 #define SRST_CORE_L2 18 398 #define SRST_CORE_L3 19 399 #define SRST_CORE_PO_L0_T 20 400 #define SRST_CORE_PO_L1 21 401 #define SRST_CORE_PO_L2 22 402 #define SRST_CORE_PO_L3 23 403 #define SRST_A_ADB400_GIC2COREL 24 404 #define SRST_A_ADB400_COREL2GIC 25 405 #define SRST_P_DBG_L 26 406 #define SRST_L2_L_T 28 407 #define SRST_ADB_L_T 29 408 #define SRST_A_RKPERF_L 30 409 #define SRST_PVTM_CORE_L 31 410 411 /* cru_softrst_con2 */ 412 #define SRST_CORE_B0_T 32 413 #define SRST_CORE_B1 33 414 #define SRST_CORE_PO_B0_T 36 415 #define SRST_CORE_PO_B1 37 416 #define SRST_A_ADB400_GIC2COREB 40 417 #define SRST_A_ADB400_COREB2GIC 41 418 #define SRST_P_DBG_B 42 419 #define SRST_L2_B_T 43 420 #define SRST_ADB_B_T 45 421 #define SRST_A_RKPERF_B 46 422 #define SRST_PVTM_CORE_B 47 423 424 /* cru_softrst_con3 */ 425 #define SRST_A_CCI_T 50 426 #define SRST_A_CCIM0_NOC_T 51 427 #define SRST_A_CCIM1_NOC_T 52 428 #define SRST_A_ADB400M_PD_CORE_B_T 53 429 #define SRST_A_ADB400M_PD_CORE_L_T 54 430 #define SRST_DBG_NOC_T 55 431 #define SRST_DBG_CXCS 56 432 #define SRST_CCI_TRACE 57 433 #define SRST_P_CCI_GRF 58 434 435 /* cru_softrst_con4 */ 436 #define SRST_A_CENTER_MAIN_NOC 64 437 #define SRST_A_CENTER_PERI_NOC 65 438 #define SRST_P_CENTER_MAIN 66 439 #define SRST_P_DDRMON 67 440 #define SRST_P_CIC 68 441 #define SRST_P_CENTER_SGRF 69 442 #define SRST_DDR0_MSCH 70 443 #define SRST_DDRCFG0_MSCH 71 444 #define SRST_DDR0 72 445 #define SRST_DDRPHY0 73 446 #define SRST_DDR1_MSCH 74 447 #define SRST_DDRCFG1_MSCH 75 448 #define SRST_DDR1 76 449 #define SRST_DDRPHY1 77 450 #define SRST_DDR_CIC 78 451 #define SRST_PVTM_DDR 79 452 453 /* cru_softrst_con5 */ 454 #define SRST_A_VCODEC_NOC 80 455 #define SRST_A_VCODEC 81 456 #define SRST_H_VCODEC_NOC 82 457 #define SRST_H_VCODEC 83 458 #define SRST_A_VDU_NOC 88 459 #define SRST_A_VDU 89 460 #define SRST_H_VDU_NOC 90 461 #define SRST_H_VDU 91 462 #define SRST_VDU_CORE 92 463 #define SRST_VDU_CA 93 464 465 /* cru_softrst_con6 */ 466 #define SRST_A_IEP_NOC 96 467 #define SRST_A_VOP_IEP 97 468 #define SRST_A_IEP 98 469 #define SRST_H_IEP_NOC 99 470 #define SRST_H_IEP 100 471 #define SRST_A_RGA_NOC 102 472 #define SRST_A_RGA 103 473 #define SRST_H_RGA_NOC 104 474 #define SRST_H_RGA 105 475 #define SRST_RGA_CORE 106 476 #define SRST_EMMC_NOC 108 477 #define SRST_EMMC 109 478 #define SRST_EMMC_GRF 110 479 480 /* cru_softrst_con7 */ 481 #define SRST_A_PERIHP_NOC 112 482 #define SRST_P_PERIHP_GRF 113 483 #define SRST_H_PERIHP_NOC 114 484 #define SRST_USBHOST0 115 485 #define SRST_HOSTC0_AUX 116 486 #define SRST_HOST0_ARB 117 487 #define SRST_USBHOST1 118 488 #define SRST_HOSTC1_AUX 119 489 #define SRST_HOST1_ARB 120 490 #define SRST_SDIO0 121 491 #define SRST_SDMMC 122 492 #define SRST_HSIC 123 493 #define SRST_HSIC_AUX 124 494 #define SRST_AHB1TOM 125 495 #define SRST_P_PERIHP_NOC 126 496 #define SRST_HSICPHY 127 497 498 /* cru_softrst_con8 */ 499 #define SRST_A_PCIE 128 500 #define SRST_P_PCIE 129 501 #define SRST_PCIE_CORE 130 502 #define SRST_PCIE_MGMT 131 503 #define SRST_PCIE_MGMT_STICKY 132 504 #define SRST_PCIE_PIPE 133 505 #define SRST_PCIE_PM 134 506 #define SRST_PCIEPHY 135 507 #define SRST_A_GMAC_NOC 136 508 #define SRST_A_GMAC 137 509 #define SRST_P_GMAC_NOC 138 510 #define SRST_P_GMAC_GRF 140 511 #define SRST_HSICPHY_POR 142 512 #define SRST_HSICPHY_UTMI 143 513 514 /* cru_softrst_con9 */ 515 #define SRST_USB2PHY0_POR 144 516 #define SRST_USB2PHY0_UTMI_PORT0 145 517 #define SRST_USB2PHY0_UTMI_PORT1 146 518 #define SRST_USB2PHY0_EHCIPHY 147 519 #define SRST_UPHY0_PIPE_L00 148 520 #define SRST_UPHY0 149 521 #define SRST_UPHY0_TCPDPWRUP 150 522 #define SRST_USB2PHY1_POR 152 523 #define SRST_USB2PHY1_UTMI_PORT0 153 524 #define SRST_USB2PHY1_UTMI_PORT1 154 525 #define SRST_USB2PHY1_EHCIPHY 155 526 #define SRST_UPHY1_PIPE_L00 156 527 #define SRST_UPHY1 157 528 #define SRST_UPHY1_TCPDPWRUP 158 529 530 /* cru_softrst_con10 */ 531 #define SRST_A_PERILP0_NOC 160 532 #define SRST_A_DCF 161 533 #define SRST_GIC500 162 534 #define SRST_DMAC0_PERILP0 163 535 #define SRST_DMAC1_PERILP0 164 536 #define SRST_TZMA 165 537 #define SRST_INTMEM 166 538 #define SRST_ADB400_MST0 167 539 #define SRST_ADB400_MST1 168 540 #define SRST_ADB400_SLV0 169 541 #define SRST_ADB400_SLV1 170 542 #define SRST_H_PERILP0 171 543 #define SRST_H_PERILP0_NOC 172 544 #define SRST_ROM 173 545 #define SRST_CRYPTO_S 174 546 #define SRST_CRYPTO_M 175 547 548 /* cru_softrst_con11 */ 549 #define SRST_P_DCF 176 550 #define SRST_CM0S_NOC 177 551 #define SRST_CM0S 178 552 #define SRST_CM0S_DBG 179 553 #define SRST_CM0S_PO 180 554 #define SRST_CRYPTO 181 555 #define SRST_P_PERILP1_SGRF 182 556 #define SRST_P_PERILP1_GRF 183 557 #define SRST_CRYPTO1_S 184 558 #define SRST_CRYPTO1_M 185 559 #define SRST_CRYPTO1 186 560 #define SRST_GIC_NOC 188 561 #define SRST_SD_NOC 189 562 #define SRST_SDIOAUDIO_BRG 190 563 564 /* cru_softrst_con12 */ 565 #define SRST_H_PERILP1 192 566 #define SRST_H_PERILP1_NOC 193 567 #define SRST_H_I2S0_8CH 194 568 #define SRST_H_I2S1_8CH 195 569 #define SRST_H_I2S2_8CH 196 570 #define SRST_H_SPDIF_8CH 197 571 #define SRST_P_PERILP1_NOC 198 572 #define SRST_P_EFUSE_1024 199 573 #define SRST_P_EFUSE_1024S 200 574 #define SRST_P_I2C0 201 575 #define SRST_P_I2C1 202 576 #define SRST_P_I2C2 203 577 #define SRST_P_I2C3 204 578 #define SRST_P_I2C4 205 579 #define SRST_P_I2C5 206 580 #define SRST_P_MAILBOX0 207 581 582 /* cru_softrst_con13 */ 583 #define SRST_P_UART0 208 584 #define SRST_P_UART1 209 585 #define SRST_P_UART2 210 586 #define SRST_P_UART3 211 587 #define SRST_P_SARADC 212 588 #define SRST_P_TSADC 213 589 #define SRST_P_SPI0 214 590 #define SRST_P_SPI1 215 591 #define SRST_P_SPI2 216 592 #define SRST_P_SPI3 217 593 #define SRST_P_SPI4 218 594 #define SRST_SPI0 219 595 #define SRST_SPI1 220 596 #define SRST_SPI2 221 597 #define SRST_SPI3 222 598 #define SRST_SPI4 223 599 600 /* cru_softrst_con14 */ 601 #define SRST_I2S0_8CH 224 602 #define SRST_I2S1_8CH 225 603 #define SRST_I2S2_8CH 226 604 #define SRST_SPDIF_8CH 227 605 #define SRST_UART0 228 606 #define SRST_UART1 229 607 #define SRST_UART2 230 608 #define SRST_UART3 231 609 #define SRST_TSADC 232 610 #define SRST_I2C0 233 611 #define SRST_I2C1 234 612 #define SRST_I2C2 235 613 #define SRST_I2C3 236 614 #define SRST_I2C4 237 615 #define SRST_I2C5 238 616 #define SRST_SDIOAUDIO_NOC 239 617 618 /* cru_softrst_con15 */ 619 #define SRST_A_VIO_NOC 240 620 #define SRST_A_HDCP_NOC 241 621 #define SRST_A_HDCP 242 622 #define SRST_H_HDCP_NOC 243 623 #define SRST_H_HDCP 244 624 #define SRST_P_HDCP_NOC 245 625 #define SRST_P_HDCP 246 626 #define SRST_P_HDMI_CTRL 247 627 #define SRST_P_DP_CTRL 248 628 #define SRST_S_DP_CTRL 249 629 #define SRST_C_DP_CTRL 250 630 #define SRST_P_MIPI_DSI0 251 631 #define SRST_P_MIPI_DSI1 252 632 #define SRST_DP_CORE 253 633 #define SRST_DP_I2S 254 634 635 /* cru_softrst_con16 */ 636 #define SRST_GASKET 256 637 #define SRST_VIO_GRF 258 638 #define SRST_DPTX_SPDIF_REC 259 639 #define SRST_HDMI_CTRL 260 640 #define SRST_HDCP_CTRL 261 641 #define SRST_A_ISP0_NOC 262 642 #define SRST_A_ISP1_NOC 263 643 #define SRST_H_ISP0_NOC 266 644 #define SRST_H_ISP1_NOC 267 645 #define SRST_H_ISP0 268 646 #define SRST_H_ISP1 269 647 #define SRST_ISP0 270 648 #define SRST_ISP1 271 649 650 /* cru_softrst_con17 */ 651 #define SRST_A_VOP0_NOC 272 652 #define SRST_A_VOP1_NOC 273 653 #define SRST_A_VOP0 274 654 #define SRST_A_VOP1 275 655 #define SRST_H_VOP0_NOC 276 656 #define SRST_H_VOP1_NOC 277 657 #define SRST_H_VOP0 278 658 #define SRST_H_VOP1 279 659 #define SRST_D_VOP0 280 660 #define SRST_D_VOP1 281 661 #define SRST_VOP0_PWM 282 662 #define SRST_VOP1_PWM 283 663 #define SRST_P_EDP_NOC 284 664 #define SRST_P_EDP_CTRL 285 665 666 /* cru_softrst_con18 */ 667 #define SRST_A_GPU 288 668 #define SRST_A_GPU_NOC 289 669 #define SRST_A_GPU_GRF 290 670 #define SRST_PVTM_GPU 291 671 #define SRST_A_USB3_NOC 292 672 #define SRST_A_USB3_OTG0 293 673 #define SRST_A_USB3_OTG1 294 674 #define SRST_A_USB3_GRF 295 675 #define SRST_PMU 296 676 677 /* cru_softrst_con19 */ 678 #define SRST_P_TIMER0_5 304 679 #define SRST_TIMER0 305 680 #define SRST_TIMER1 306 681 #define SRST_TIMER2 307 682 #define SRST_TIMER3 308 683 #define SRST_TIMER4 309 684 #define SRST_TIMER5 310 685 #define SRST_P_TIMER6_11 311 686 #define SRST_TIMER6 312 687 #define SRST_TIMER7 313 688 #define SRST_TIMER8 314 689 #define SRST_TIMER9 315 690 #define SRST_TIMER10 316 691 #define SRST_TIMER11 317 692 #define SRST_P_INTR_ARB_PMU 318 693 #define SRST_P_ALIVE_SGRF 319 694 695 /* cru_softrst_con20 */ 696 #define SRST_P_GPIO2 320 697 #define SRST_P_GPIO3 321 698 #define SRST_P_GPIO4 322 699 #define SRST_P_GRF 323 700 #define SRST_P_ALIVE_NOC 324 701 #define SRST_P_WDT0 325 702 #define SRST_P_WDT1 326 703 #define SRST_P_INTR_ARB 327 704 #define SRST_P_UPHY0_DPTX 328 705 #define SRST_P_UPHY0_APB 330 706 #define SRST_P_UPHY0_TCPHY 332 707 #define SRST_P_UPHY1_TCPHY 333 708 #define SRST_P_UPHY0_TCPDCTRL 334 709 #define SRST_P_UPHY1_TCPDCTRL 335 710 711 /* pmu soft-reset indices */ 712 713 /* pmu_cru_softrst_con0 */ 714 #define SRST_P_NOC 0 715 #define SRST_P_INTMEM 1 716 #define SRST_H_CM0S 2 717 #define SRST_H_CM0S_NOC 3 718 #define SRST_DBG_CM0S 4 719 #define SRST_PO_CM0S 5 720 #define SRST_P_SPI6 6 721 #define SRST_SPI6 7 722 #define SRST_P_TIMER_0_1 8 723 #define SRST_P_TIMER_0 9 724 #define SRST_P_TIMER_1 10 725 #define SRST_P_UART4 11 726 #define SRST_UART4 12 727 #define SRST_P_WDT 13 728 729 /* pmu_cru_softrst_con1 */ 730 #define SRST_P_I2C6 16 731 #define SRST_P_I2C7 17 732 #define SRST_P_I2C8 18 733 #define SRST_P_MAILBOX 19 734 #define SRST_P_RKPWM 20 735 #define SRST_P_PMUGRF 21 736 #define SRST_P_SGRF 22 737 #define SRST_P_GPIO0 23 738 #define SRST_P_GPIO1 24 739 #define SRST_P_CRU 25 740 #define SRST_P_INTR 26 741 #define SRST_PVTM 27 742 #define SRST_I2C6 28 743 #define SRST_I2C7 29 744 #define SRST_I2C8 30 745 746 #endif 747