1*0d218efeSMarek Vasut /* SPDX-License-Identifier: GPL-2.0 */ 2*0d218efeSMarek Vasut /* 3*0d218efeSMarek Vasut * Copyright (C) 2018 Renesas Electronics Corp. 4*0d218efeSMarek Vasut */ 5*0d218efeSMarek Vasut #ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ 6*0d218efeSMarek Vasut #define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ 7*0d218efeSMarek Vasut 8*0d218efeSMarek Vasut #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*0d218efeSMarek Vasut 10*0d218efeSMarek Vasut /* r8a77990 CPG Core Clocks */ 11*0d218efeSMarek Vasut #define R8A77990_CLK_Z2 0 12*0d218efeSMarek Vasut #define R8A77990_CLK_ZR 1 13*0d218efeSMarek Vasut #define R8A77990_CLK_ZG 2 14*0d218efeSMarek Vasut #define R8A77990_CLK_ZTR 3 15*0d218efeSMarek Vasut #define R8A77990_CLK_ZT 4 16*0d218efeSMarek Vasut #define R8A77990_CLK_ZX 5 17*0d218efeSMarek Vasut #define R8A77990_CLK_S0D1 6 18*0d218efeSMarek Vasut #define R8A77990_CLK_S0D3 7 19*0d218efeSMarek Vasut #define R8A77990_CLK_S0D6 8 20*0d218efeSMarek Vasut #define R8A77990_CLK_S0D12 9 21*0d218efeSMarek Vasut #define R8A77990_CLK_S0D24 10 22*0d218efeSMarek Vasut #define R8A77990_CLK_S1D1 11 23*0d218efeSMarek Vasut #define R8A77990_CLK_S1D2 12 24*0d218efeSMarek Vasut #define R8A77990_CLK_S1D4 13 25*0d218efeSMarek Vasut #define R8A77990_CLK_S2D1 14 26*0d218efeSMarek Vasut #define R8A77990_CLK_S2D2 15 27*0d218efeSMarek Vasut #define R8A77990_CLK_S2D4 16 28*0d218efeSMarek Vasut #define R8A77990_CLK_S3D1 17 29*0d218efeSMarek Vasut #define R8A77990_CLK_S3D2 18 30*0d218efeSMarek Vasut #define R8A77990_CLK_S3D4 19 31*0d218efeSMarek Vasut #define R8A77990_CLK_S0D6C 20 32*0d218efeSMarek Vasut #define R8A77990_CLK_S3D1C 21 33*0d218efeSMarek Vasut #define R8A77990_CLK_S3D2C 22 34*0d218efeSMarek Vasut #define R8A77990_CLK_S3D4C 23 35*0d218efeSMarek Vasut #define R8A77990_CLK_LB 24 36*0d218efeSMarek Vasut #define R8A77990_CLK_CL 25 37*0d218efeSMarek Vasut #define R8A77990_CLK_ZB3 26 38*0d218efeSMarek Vasut #define R8A77990_CLK_ZB3D2 27 39*0d218efeSMarek Vasut #define R8A77990_CLK_CR 28 40*0d218efeSMarek Vasut #define R8A77990_CLK_CRD2 29 41*0d218efeSMarek Vasut #define R8A77990_CLK_SD0H 30 42*0d218efeSMarek Vasut #define R8A77990_CLK_SD0 31 43*0d218efeSMarek Vasut #define R8A77990_CLK_SD1H 32 44*0d218efeSMarek Vasut #define R8A77990_CLK_SD1 33 45*0d218efeSMarek Vasut #define R8A77990_CLK_SD3H 34 46*0d218efeSMarek Vasut #define R8A77990_CLK_SD3 35 47*0d218efeSMarek Vasut #define R8A77990_CLK_RPC 36 48*0d218efeSMarek Vasut #define R8A77990_CLK_RPCD2 37 49*0d218efeSMarek Vasut #define R8A77990_CLK_ZA2 38 50*0d218efeSMarek Vasut #define R8A77990_CLK_ZA8 39 51*0d218efeSMarek Vasut #define R8A77990_CLK_Z2D 40 52*0d218efeSMarek Vasut #define R8A77990_CLK_CANFD 41 53*0d218efeSMarek Vasut #define R8A77990_CLK_MSO 42 54*0d218efeSMarek Vasut #define R8A77990_CLK_R 43 55*0d218efeSMarek Vasut #define R8A77990_CLK_OSC 44 56*0d218efeSMarek Vasut #define R8A77990_CLK_LV0 45 57*0d218efeSMarek Vasut #define R8A77990_CLK_LV1 46 58*0d218efeSMarek Vasut #define R8A77990_CLK_CSI0 47 59*0d218efeSMarek Vasut #define R8A77990_CLK_POST3 48 60*0d218efeSMarek Vasut #define R8A77990_CLK_CP 49 61*0d218efeSMarek Vasut #define R8A77990_CLK_CPEX 50 62*0d218efeSMarek Vasut 63*0d218efeSMarek Vasut #endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ 64