1 /* 2 * Copyright (C) 2015 Renesas Electronics Corp. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ 10 #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ 11 12 #include <dt-bindings/clock/renesas-cpg-mssr.h> 13 14 /* r8a7795 CPG Core Clocks */ 15 #define R8A7795_CLK_Z 0 16 #define R8A7795_CLK_Z2 1 17 #define R8A7795_CLK_ZR 2 18 #define R8A7795_CLK_ZG 3 19 #define R8A7795_CLK_ZTR 4 20 #define R8A7795_CLK_ZTRD2 5 21 #define R8A7795_CLK_ZT 6 22 #define R8A7795_CLK_ZX 7 23 #define R8A7795_CLK_S0D1 8 24 #define R8A7795_CLK_S0D4 9 25 #define R8A7795_CLK_S1D1 10 26 #define R8A7795_CLK_S1D2 11 27 #define R8A7795_CLK_S1D4 12 28 #define R8A7795_CLK_S2D1 13 29 #define R8A7795_CLK_S2D2 14 30 #define R8A7795_CLK_S2D4 15 31 #define R8A7795_CLK_S3D1 16 32 #define R8A7795_CLK_S3D2 17 33 #define R8A7795_CLK_S3D4 18 34 #define R8A7795_CLK_LB 19 35 #define R8A7795_CLK_CL 20 36 #define R8A7795_CLK_ZB3 21 37 #define R8A7795_CLK_ZB3D2 22 38 #define R8A7795_CLK_CR 23 39 #define R8A7795_CLK_CRD2 24 40 #define R8A7795_CLK_SD0H 25 41 #define R8A7795_CLK_SD0 26 42 #define R8A7795_CLK_SD1H 27 43 #define R8A7795_CLK_SD1 28 44 #define R8A7795_CLK_SD2H 29 45 #define R8A7795_CLK_SD2 30 46 #define R8A7795_CLK_SD3H 31 47 #define R8A7795_CLK_SD3 32 48 #define R8A7795_CLK_SSP2 33 49 #define R8A7795_CLK_SSP1 34 50 #define R8A7795_CLK_SSPRS 35 51 #define R8A7795_CLK_RPC 36 52 #define R8A7795_CLK_RPCD2 37 53 #define R8A7795_CLK_MSO 38 54 #define R8A7795_CLK_CANFD 39 55 #define R8A7795_CLK_HDMI 40 56 #define R8A7795_CLK_CSI0 41 57 #define R8A7795_CLK_CSIREF 42 58 #define R8A7795_CLK_CP 43 59 #define R8A7795_CLK_CPEX 44 60 #define R8A7795_CLK_R 45 61 #define R8A7795_CLK_OSC 46 62 63 /* r8a7795 ES2.0 CPG Core Clocks */ 64 #define R8A7795_CLK_S0D2 47 65 #define R8A7795_CLK_S0D3 48 66 #define R8A7795_CLK_S0D6 49 67 #define R8A7795_CLK_S0D8 50 68 #define R8A7795_CLK_S0D12 51 69 70 #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ 71