1 /*
2  * Copyright (C) 2015 Renesas Electronics Corp.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  */
9 
10 #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
11 #define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
12 
13 #include <dt-bindings/clock/renesas-cpg-mssr.h>
14 
15 /* r8a7790 CPG Core Clocks */
16 #define R8A7790_CLK_Z			0
17 #define R8A7790_CLK_Z2			1
18 #define R8A7790_CLK_ZG			2
19 #define R8A7790_CLK_ZTR			3
20 #define R8A7790_CLK_ZTRD2		4
21 #define R8A7790_CLK_ZT			5
22 #define R8A7790_CLK_ZX			6
23 #define R8A7790_CLK_ZS			7
24 #define R8A7790_CLK_HP			8
25 #define R8A7790_CLK_I			9
26 #define R8A7790_CLK_B			10
27 #define R8A7790_CLK_LB			11
28 #define R8A7790_CLK_P			12
29 #define R8A7790_CLK_CL			13
30 #define R8A7790_CLK_M2			14
31 #define R8A7790_CLK_ADSP		15
32 #define R8A7790_CLK_IMP			16
33 #define R8A7790_CLK_ZB3			17
34 #define R8A7790_CLK_ZB3D2		18
35 #define R8A7790_CLK_DDR			19
36 #define R8A7790_CLK_SDH			20
37 #define R8A7790_CLK_SD0			21
38 #define R8A7790_CLK_SD1			22
39 #define R8A7790_CLK_SD2			23
40 #define R8A7790_CLK_SD3			24
41 #define R8A7790_CLK_MMC0		25
42 #define R8A7790_CLK_MMC1		26
43 #define R8A7790_CLK_MP			27
44 #define R8A7790_CLK_SSP			28
45 #define R8A7790_CLK_SSPRS		29
46 #define R8A7790_CLK_QSPI		30
47 #define R8A7790_CLK_CP			31
48 #define R8A7790_CLK_RCAN		32
49 #define R8A7790_CLK_R			33
50 #define R8A7790_CLK_OSC			34
51 
52 #endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
53