1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_MT2701_H 7 #define _DT_BINDINGS_CLK_MT2701_H 8 9 /* TOPCKGEN */ 10 #define CLK_TOP_FCLKS_OFF 0 11 12 #define CLK_TOP_DPI 0 13 #define CLK_TOP_DMPLL 1 14 #define CLK_TOP_VENCPLL 2 15 #define CLK_TOP_HDMI_0_PIX340M 3 16 #define CLK_TOP_HDMI_0_DEEP340M 4 17 #define CLK_TOP_HDMI_0_PLL340M 5 18 #define CLK_TOP_HADDS2_FB 6 19 #define CLK_TOP_WBG_DIG_416M 7 20 #define CLK_TOP_DSI0_LNTC_DSI 8 21 #define CLK_TOP_HDMI_SCL_RX 9 22 #define CLK_TOP_32K_EXTERNAL 10 23 #define CLK_TOP_HDMITX_CLKDIG_CTS 11 24 #define CLK_TOP_AUD_EXT1 12 25 #define CLK_TOP_AUD_EXT2 13 26 #define CLK_TOP_NFI1X_PAD 14 27 28 #define CLK_TOP_SYSPLL 15 29 #define CLK_TOP_SYSPLL_D2 16 30 #define CLK_TOP_SYSPLL_D3 17 31 #define CLK_TOP_SYSPLL_D5 18 32 #define CLK_TOP_SYSPLL_D7 19 33 #define CLK_TOP_SYSPLL1_D2 20 34 #define CLK_TOP_SYSPLL1_D4 21 35 #define CLK_TOP_SYSPLL1_D8 22 36 #define CLK_TOP_SYSPLL1_D16 23 37 #define CLK_TOP_SYSPLL2_D2 24 38 #define CLK_TOP_SYSPLL2_D4 25 39 #define CLK_TOP_SYSPLL2_D8 26 40 #define CLK_TOP_SYSPLL3_D2 27 41 #define CLK_TOP_SYSPLL3_D4 28 42 #define CLK_TOP_SYSPLL4_D2 29 43 #define CLK_TOP_SYSPLL4_D4 30 44 #define CLK_TOP_UNIVPLL 31 45 #define CLK_TOP_UNIVPLL_D2 32 46 #define CLK_TOP_UNIVPLL_D3 33 47 #define CLK_TOP_UNIVPLL_D5 34 48 #define CLK_TOP_UNIVPLL_D7 35 49 #define CLK_TOP_UNIVPLL_D26 36 50 #define CLK_TOP_UNIVPLL_D52 37 51 #define CLK_TOP_UNIVPLL_D108 38 52 #define CLK_TOP_USB_PHY48M 39 53 #define CLK_TOP_UNIVPLL1_D2 40 54 #define CLK_TOP_UNIVPLL1_D4 41 55 #define CLK_TOP_UNIVPLL1_D8 42 56 #define CLK_TOP_UNIVPLL2_D2 43 57 #define CLK_TOP_UNIVPLL2_D4 44 58 #define CLK_TOP_UNIVPLL2_D8 45 59 #define CLK_TOP_UNIVPLL2_D16 46 60 #define CLK_TOP_UNIVPLL2_D32 47 61 #define CLK_TOP_UNIVPLL3_D2 48 62 #define CLK_TOP_UNIVPLL3_D4 49 63 #define CLK_TOP_UNIVPLL3_D8 50 64 #define CLK_TOP_MSDCPLL 51 65 #define CLK_TOP_MSDCPLL_D2 52 66 #define CLK_TOP_MSDCPLL_D4 53 67 #define CLK_TOP_MSDCPLL_D8 54 68 #define CLK_TOP_MMPLL 55 69 #define CLK_TOP_MMPLL_D2 56 70 #define CLK_TOP_DMPLL_D2 57 71 #define CLK_TOP_DMPLL_D4 58 72 #define CLK_TOP_DMPLL_X2 59 73 #define CLK_TOP_TVDPLL 60 74 #define CLK_TOP_TVDPLL_D2 61 75 #define CLK_TOP_TVDPLL_D4 62 76 #define CLK_TOP_VDECPLL 63 77 #define CLK_TOP_TVD2PLL 64 78 #define CLK_TOP_TVD2PLL_D2 65 79 #define CLK_TOP_MIPIPLL 66 80 #define CLK_TOP_MIPIPLL_D2 67 81 #define CLK_TOP_MIPIPLL_D4 68 82 #define CLK_TOP_HDMIPLL 69 83 #define CLK_TOP_HDMIPLL_D2 70 84 #define CLK_TOP_HDMIPLL_D3 71 85 #define CLK_TOP_ARMPLL_1P3G 72 86 #define CLK_TOP_AUDPLL 73 87 #define CLK_TOP_AUDPLL_D4 74 88 #define CLK_TOP_AUDPLL_D8 75 89 #define CLK_TOP_AUDPLL_D16 76 90 #define CLK_TOP_AUDPLL_D24 77 91 #define CLK_TOP_AUD1PLL_98M 78 92 #define CLK_TOP_AUD2PLL_90M 79 93 #define CLK_TOP_HADDS2PLL_98M 80 94 #define CLK_TOP_HADDS2PLL_294M 81 95 #define CLK_TOP_ETHPLL_500M 82 96 #define CLK_TOP_CLK26M_D8 83 97 #define CLK_TOP_32K_INTERNAL 84 98 #define CLK_TOP_AXISEL_D4 85 99 #define CLK_TOP_8BDAC 86 100 101 #define CLK_TOP_AXI_SEL 87 102 #define CLK_TOP_MEM_SEL 88 103 #define CLK_TOP_DDRPHYCFG_SEL 89 104 #define CLK_TOP_MM_SEL 90 105 #define CLK_TOP_PWM_SEL 91 106 #define CLK_TOP_VDEC_SEL 92 107 #define CLK_TOP_MFG_SEL 93 108 #define CLK_TOP_CAMTG_SEL 94 109 #define CLK_TOP_UART_SEL 95 110 #define CLK_TOP_SPI0_SEL 96 111 #define CLK_TOP_USB20_SEL 97 112 #define CLK_TOP_MSDC30_0_SEL 98 113 #define CLK_TOP_MSDC30_1_SEL 99 114 #define CLK_TOP_MSDC30_2_SEL 100 115 #define CLK_TOP_AUDIO_SEL 101 116 #define CLK_TOP_AUDINTBUS_SEL 102 117 #define CLK_TOP_PMICSPI_SEL 103 118 #define CLK_TOP_SCP_SEL 104 119 #define CLK_TOP_DPI0_SEL 105 120 #define CLK_TOP_DPI1_SEL 106 121 #define CLK_TOP_TVE_SEL 107 122 #define CLK_TOP_HDMI_SEL 108 123 #define CLK_TOP_APLL_SEL 109 124 #define CLK_TOP_RTC_SEL 110 125 #define CLK_TOP_NFI2X_SEL 111 126 #define CLK_TOP_EMMC_HCLK_SEL 112 127 #define CLK_TOP_FLASH_SEL 113 128 #define CLK_TOP_DI_SEL 114 129 #define CLK_TOP_NR_SEL 115 130 #define CLK_TOP_OSD_SEL 116 131 #define CLK_TOP_HDMIRX_BIST_SEL 117 132 #define CLK_TOP_INTDIR_SEL 118 133 #define CLK_TOP_ASM_I_SEL 119 134 #define CLK_TOP_ASM_M_SEL 120 135 #define CLK_TOP_ASM_H_SEL 121 136 #define CLK_TOP_MS_CARD_SEL 122 137 #define CLK_TOP_ETHIF_SEL 123 138 #define CLK_TOP_HDMIRX26_24_SEL 124 139 #define CLK_TOP_MSDC30_3_SEL 125 140 #define CLK_TOP_CMSYS_SEL 126 141 #define CLK_TOP_SPI1_SEL 127 142 #define CLK_TOP_SPI2_SEL 128 143 #define CLK_TOP_8BDAC_SEL 129 144 #define CLK_TOP_AUD2DVD_SEL 130 145 #define CLK_TOP_PADMCLK_SEL 131 146 #define CLK_TOP_AUD_MUX1_SEL 132 147 #define CLK_TOP_AUD_MUX2_SEL 133 148 #define CLK_TOP_AUDPLL_MUX_SEL 134 149 #define CLK_TOP_AUD_K1_SRC_SEL 135 150 #define CLK_TOP_AUD_K2_SRC_SEL 136 151 #define CLK_TOP_AUD_K3_SRC_SEL 137 152 #define CLK_TOP_AUD_K4_SRC_SEL 138 153 #define CLK_TOP_AUD_K5_SRC_SEL 139 154 #define CLK_TOP_AUD_K6_SRC_SEL 140 155 156 #define CLK_TOP_AUD_EXTCK1_DIV 141 157 #define CLK_TOP_AUD_EXTCK2_DIV 142 158 #define CLK_TOP_AUD_MUX1_DIV 143 159 #define CLK_TOP_AUD_MUX2_DIV 144 160 #define CLK_TOP_AUD_K1_SRC_DIV 145 161 #define CLK_TOP_AUD_K2_SRC_DIV 146 162 #define CLK_TOP_AUD_K3_SRC_DIV 147 163 #define CLK_TOP_AUD_K4_SRC_DIV 148 164 #define CLK_TOP_AUD_K5_SRC_DIV 149 165 #define CLK_TOP_AUD_K6_SRC_DIV 150 166 #define CLK_TOP_AUD_48K_TIMING 151 167 #define CLK_TOP_AUD_44K_TIMING 152 168 #define CLK_TOP_AUD_I2S1_MCLK 153 169 #define CLK_TOP_AUD_I2S2_MCLK 154 170 #define CLK_TOP_AUD_I2S3_MCLK 155 171 #define CLK_TOP_AUD_I2S4_MCLK 156 172 #define CLK_TOP_AUD_I2S5_MCLK 157 173 #define CLK_TOP_AUD_I2S6_MCLK 158 174 #define CLK_TOP_NR 159 175 176 /* APMIXEDSYS */ 177 #define CLK_APMIXED_ARMPLL 0 178 #define CLK_APMIXED_MAINPLL 1 179 #define CLK_APMIXED_UNIVPLL 2 180 #define CLK_APMIXED_MMPLL 3 181 #define CLK_APMIXED_MSDCPLL 4 182 #define CLK_APMIXED_TVDPLL 5 183 #define CLK_APMIXED_AUD1PLL 6 184 #define CLK_APMIXED_TRGPLL 7 185 #define CLK_APMIXED_ETHPLL 8 186 #define CLK_APMIXED_VDECPLL 9 187 #define CLK_APMIXED_HADDS2PLL 10 188 #define CLK_APMIXED_AUD2PLL 11 189 #define CLK_APMIXED_TVD2PLL 12 190 #define CLK_APMIXED_NR 13 191 192 /* INFRACFG */ 193 #define CLK_INFRA_DBG 0 194 #define CLK_INFRA_SMI 1 195 #define CLK_INFRA_QAXI_CM4 2 196 #define CLK_INFRA_AUD_SPLIN_B 3 197 #define CLK_INFRA_AUDIO 4 198 #define CLK_INFRA_EFUSE 5 199 #define CLK_INFRA_L2C_SRAM 6 200 #define CLK_INFRA_M4U 7 201 #define CLK_INFRA_CONNMCU 8 202 #define CLK_INFRA_TRNG 9 203 #define CLK_INFRA_RAMBUFIF 10 204 #define CLK_INFRA_CPUM 11 205 #define CLK_INFRA_KP 12 206 #define CLK_INFRA_CEC 13 207 #define CLK_INFRA_IRRX 14 208 #define CLK_INFRA_PMICSPI 15 209 #define CLK_INFRA_PMICWRAP 16 210 #define CLK_INFRA_DDCCI 17 211 #define CLK_INFRA_CPUSEL 18 212 #define CLK_INFRA_NR 19 213 214 /* PERICFG */ 215 #define CLK_PERI_NFI 0 216 #define CLK_PERI_THERM 1 217 #define CLK_PERI_PWM1 2 218 #define CLK_PERI_PWM2 3 219 #define CLK_PERI_PWM3 4 220 #define CLK_PERI_PWM4 5 221 #define CLK_PERI_PWM5 6 222 #define CLK_PERI_PWM6 7 223 #define CLK_PERI_PWM7 8 224 #define CLK_PERI_PWM 9 225 #define CLK_PERI_USB0 10 226 #define CLK_PERI_USB1 11 227 #define CLK_PERI_AP_DMA 12 228 #define CLK_PERI_MSDC30_0 13 229 #define CLK_PERI_MSDC30_1 14 230 #define CLK_PERI_MSDC30_2 15 231 #define CLK_PERI_MSDC30_3 16 232 #define CLK_PERI_MSDC50_3 17 233 #define CLK_PERI_NLI 18 234 #define CLK_PERI_UART0 19 235 #define CLK_PERI_UART1 20 236 #define CLK_PERI_UART2 21 237 #define CLK_PERI_UART3 22 238 #define CLK_PERI_BTIF 23 239 #define CLK_PERI_I2C0 24 240 #define CLK_PERI_I2C1 25 241 #define CLK_PERI_I2C2 26 242 #define CLK_PERI_I2C3 27 243 #define CLK_PERI_AUXADC 28 244 #define CLK_PERI_SPI0 39 245 #define CLK_PERI_ETH 30 246 #define CLK_PERI_USB0_MCU 31 247 248 #define CLK_PERI_USB1_MCU 32 249 #define CLK_PERI_USB_SLV 33 250 #define CLK_PERI_GCPU 34 251 #define CLK_PERI_NFI_ECC 35 252 #define CLK_PERI_NFI_PAD 36 253 #define CLK_PERI_FLASH 37 254 #define CLK_PERI_HOST89_INT 38 255 #define CLK_PERI_HOST89_SPI 39 256 #define CLK_PERI_HOST89_DVD 40 257 #define CLK_PERI_SPI1 41 258 #define CLK_PERI_SPI2 42 259 #define CLK_PERI_FCI 43 260 #define CLK_PERI_NR 44 261 262 /* AUDIO */ 263 #define CLK_AUD_AFE 0 264 #define CLK_AUD_LRCK_DETECT 1 265 #define CLK_AUD_I2S 2 266 #define CLK_AUD_APLL_TUNER 3 267 #define CLK_AUD_HDMI 4 268 #define CLK_AUD_SPDF 5 269 #define CLK_AUD_SPDF2 6 270 #define CLK_AUD_APLL 7 271 #define CLK_AUD_TML 8 272 #define CLK_AUD_AHB_IDLE_EXT 9 273 #define CLK_AUD_AHB_IDLE_INT 10 274 275 #define CLK_AUD_I2SIN1 11 276 #define CLK_AUD_I2SIN2 12 277 #define CLK_AUD_I2SIN3 13 278 #define CLK_AUD_I2SIN4 14 279 #define CLK_AUD_I2SIN5 15 280 #define CLK_AUD_I2SIN6 16 281 #define CLK_AUD_I2SO1 17 282 #define CLK_AUD_I2SO2 18 283 #define CLK_AUD_I2SO3 19 284 #define CLK_AUD_I2SO4 20 285 #define CLK_AUD_I2SO5 21 286 #define CLK_AUD_I2SO6 22 287 #define CLK_AUD_ASRCI1 23 288 #define CLK_AUD_ASRCI2 24 289 #define CLK_AUD_ASRCO1 25 290 #define CLK_AUD_ASRCO2 26 291 #define CLK_AUD_ASRC11 27 292 #define CLK_AUD_ASRC12 28 293 #define CLK_AUD_HDMIRX 29 294 #define CLK_AUD_INTDIR 30 295 #define CLK_AUD_A1SYS 31 296 #define CLK_AUD_A2SYS 32 297 #define CLK_AUD_AFE_CONN 33 298 #define CLK_AUD_AFE_PCMIF 34 299 #define CLK_AUD_AFE_MRGIF 35 300 301 #define CLK_AUD_MMIF_UL1 36 302 #define CLK_AUD_MMIF_UL2 37 303 #define CLK_AUD_MMIF_UL3 38 304 #define CLK_AUD_MMIF_UL4 39 305 #define CLK_AUD_MMIF_UL5 40 306 #define CLK_AUD_MMIF_UL6 41 307 #define CLK_AUD_MMIF_DL1 42 308 #define CLK_AUD_MMIF_DL2 43 309 #define CLK_AUD_MMIF_DL3 44 310 #define CLK_AUD_MMIF_DL4 45 311 #define CLK_AUD_MMIF_DL5 46 312 #define CLK_AUD_MMIF_DL6 47 313 #define CLK_AUD_MMIF_DLMCH 48 314 #define CLK_AUD_MMIF_ARB1 49 315 #define CLK_AUD_MMIF_AWB1 50 316 #define CLK_AUD_MMIF_AWB2 51 317 #define CLK_AUD_MMIF_DAI 52 318 319 #define CLK_AUD_DMIC1 53 320 #define CLK_AUD_DMIC2 54 321 #define CLK_AUD_ASRCI3 55 322 #define CLK_AUD_ASRCI4 56 323 #define CLK_AUD_ASRCI5 57 324 #define CLK_AUD_ASRCI6 58 325 #define CLK_AUD_ASRCO3 59 326 #define CLK_AUD_ASRCO4 60 327 #define CLK_AUD_ASRCO5 61 328 #define CLK_AUD_ASRCO6 62 329 #define CLK_AUD_MEM_ASRC1 63 330 #define CLK_AUD_MEM_ASRC2 64 331 #define CLK_AUD_MEM_ASRC3 65 332 #define CLK_AUD_MEM_ASRC4 66 333 #define CLK_AUD_MEM_ASRC5 67 334 #define CLK_AUD_DSD_ENC 68 335 #define CLK_AUD_ASRC_BRG 60 336 #define CLK_AUD_NR 70 337 338 /* MMSYS */ 339 #define CLK_MM_SMI_COMMON 0 340 #define CLK_MM_SMI_LARB0 1 341 #define CLK_MM_CMDQ 2 342 #define CLK_MM_MUTEX 3 343 #define CLK_MM_DISP_COLOR 4 344 #define CLK_MM_DISP_BLS 5 345 #define CLK_MM_DISP_WDMA 6 346 #define CLK_MM_DISP_RDMA 7 347 #define CLK_MM_DISP_OVL 8 348 #define CLK_MM_MDP_TDSHP 9 349 #define CLK_MM_MDP_WROT 10 350 #define CLK_MM_MDP_WDMA 11 351 #define CLK_MM_MDP_RSZ1 12 352 #define CLK_MM_MDP_RSZ0 13 353 #define CLK_MM_MDP_RDMA 14 354 #define CLK_MM_MDP_BLS_26M 15 355 #define CLK_MM_CAM_MDP 16 356 #define CLK_MM_FAKE_ENG 17 357 #define CLK_MM_MUTEX_32K 18 358 #define CLK_MM_DISP_RDMA1 19 359 #define CLK_MM_DISP_UFOE 20 360 361 #define CLK_MM_DSI_ENGINE 21 362 #define CLK_MM_DSI_DIG 22 363 #define CLK_MM_DPI_DIGL 23 364 #define CLK_MM_DPI_ENGINE 24 365 #define CLK_MM_DPI1_DIGL 25 366 #define CLK_MM_DPI1_ENGINE 26 367 #define CLK_MM_TVE_OUTPUT 27 368 #define CLK_MM_TVE_INPUT 28 369 #define CLK_MM_HDMI_PIXEL 29 370 #define CLK_MM_HDMI_PLL 30 371 #define CLK_MM_HDMI_AUDIO 31 372 #define CLK_MM_HDMI_SPDIF 32 373 #define CLK_MM_TVE_FMM 33 374 #define CLK_MM_NR 34 375 376 /* IMGSYS */ 377 #define CLK_IMG_SMI_COMM 0 378 #define CLK_IMG_RESZ 1 379 #define CLK_IMG_JPGDEC_SMI 2 380 #define CLK_IMG_JPGDEC 3 381 #define CLK_IMG_VENC_LT 4 382 #define CLK_IMG_VENC 5 383 #define CLK_IMG_NR 6 384 385 /* VDEC */ 386 #define CLK_VDEC_CKGEN 0 387 #define CLK_VDEC_LARB 1 388 #define CLK_VDEC_NR 2 389 390 /* HIFSYS */ 391 #define CLK_HIFSYS_USB0PHY 0 392 #define CLK_HIFSYS_USB1PHY 1 393 #define CLK_HIFSYS_PCIE0 2 394 #define CLK_HIFSYS_PCIE1 3 395 #define CLK_HIFSYS_PCIE2 4 396 #define CLK_HIFSYS_NR 5 397 398 /* ETHSYS */ 399 #define CLK_ETHSYS_HSDMA 0 400 #define CLK_ETHSYS_ESW 1 401 #define CLK_ETHSYS_GP2 2 402 #define CLK_ETHSYS_GP1 3 403 #define CLK_ETHSYS_PCM 4 404 #define CLK_ETHSYS_GDMA 5 405 #define CLK_ETHSYS_I2S 6 406 #define CLK_ETHSYS_CRYPTO 7 407 #define CLK_ETHSYS_NR 8 408 409 /* G3DSYS */ 410 #define CLK_G3DSYS_CORE 0 411 #define CLK_G3DSYS_NR 1 412 413 #endif /* _DT_BINDINGS_CLK_MT2701_H */ 414