1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Google Inc. 4 */ 5 6 /* Core Clocks */ 7 #define PLL_HPLL 1 8 #define PLL_DPLL 2 9 #define PLL_D2PLL 3 10 #define PLL_MPLL 4 11 #define ARMCLK 5 12 13 14 /* Bus Clocks, derived from core clocks */ 15 #define BCLK_PCLK 101 16 #define BCLK_LHCLK 102 17 #define BCLK_MACCLK 103 18 #define BCLK_SDCLK 104 19 #define BCLK_ARMCLK 105 20 #define BCLK_HCLK 106 21 22 #define MCLK_DDR 201 23 24 /* Special clocks */ 25 #define PCLK_UART1 501 26 #define PCLK_UART2 502 27 #define PCLK_UART3 503 28 #define PCLK_UART4 504 29 #define PCLK_UART5 505 30 #define PCLK_MAC1 506 31 #define PCLK_MAC2 507 32