1 /* 2 * Copyright (c) 2013 Google, Inc 3 * 4 * (C) Copyright 2012 5 * Pavel Herrmann <morpheus.ibis@gmail.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _DM_UCLASS_ID_H 11 #define _DM_UCLASS_ID_H 12 13 /* TODO(sjg@chromium.org): this could be compile-time generated */ 14 enum uclass_id { 15 /* These are used internally by driver model */ 16 UCLASS_ROOT = 0, 17 UCLASS_DEMO, 18 UCLASS_TEST, 19 UCLASS_TEST_FDT, 20 UCLASS_TEST_BUS, 21 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ 22 UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ 23 UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ 24 UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ 25 UCLASS_SIMPLE_BUS, /* bus with child devices */ 26 27 /* U-Boot uclasses start here - in alphabetical order */ 28 UCLASS_CPU, /* CPU, typically part of an SoC */ 29 UCLASS_CROS_EC, /* Chrome OS EC */ 30 UCLASS_DISPLAY_PORT, /* Display port video */ 31 UCLASS_ETH, /* Ethernet device */ 32 UCLASS_GPIO, /* Bank of general-purpose I/O pins */ 33 UCLASS_I2C, /* I2C bus */ 34 UCLASS_I2C_EEPROM, /* I2C EEPROM device */ 35 UCLASS_I2C_GENERIC, /* Generic I2C device */ 36 UCLASS_LPC, /* x86 'low pin count' interface */ 37 UCLASS_MASS_STORAGE, /* Mass storage device */ 38 UCLASS_MOD_EXP, /* RSA Mod Exp device */ 39 UCLASS_PCH, /* x86 platform controller hub */ 40 UCLASS_PCI, /* PCI bus */ 41 UCLASS_PCI_GENERIC, /* Generic PCI bus device */ 42 UCLASS_RTC, /* Real time clock device */ 43 UCLASS_SERIAL, /* Serial UART */ 44 UCLASS_SPI, /* SPI bus */ 45 UCLASS_SPI_GENERIC, /* Generic SPI flash target */ 46 UCLASS_SPI_FLASH, /* SPI flash */ 47 UCLASS_THERMAL, /* Thermal sensor */ 48 UCLASS_USB, /* USB bus */ 49 UCLASS_USB_DEV_GENERIC, /* USB generic device */ 50 UCLASS_USB_HUB, /* USB hub */ 51 52 /* Power Management */ 53 UCLASS_PMIC, /* PMIC I/O device */ 54 UCLASS_REGULATOR, /* REGULATOR device */ 55 56 UCLASS_COUNT, 57 UCLASS_INVALID = -1, 58 }; 59 60 #endif 61