1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DDR_SPD_H_ 8 #define _DDR_SPD_H_ 9 10 /* 11 * Format from "JEDEC Standard No. 21-C, 12 * Appendix D: Rev 1.0: SPD's for DDR SDRAM 13 */ 14 typedef struct ddr1_spd_eeprom_s { 15 unsigned char info_size; /* 0 # bytes written into serial memory */ 16 unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 17 unsigned char mem_type; /* 2 Fundamental memory type */ 18 unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 19 unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 20 unsigned char nrows; /* 5 Number of DIMM Banks */ 21 unsigned char dataw_lsb; /* 6 Data Width of this assembly */ 22 unsigned char dataw_msb; /* 7 ... Data Width continuation */ 23 unsigned char voltage; /* 8 Voltage intf std of this assembly */ 24 unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 25 unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 26 unsigned char config; /* 11 DIMM Configuration type */ 27 unsigned char refresh; /* 12 Refresh Rate/Type */ 28 unsigned char primw; /* 13 Primary SDRAM Width */ 29 unsigned char ecw; /* 14 Error Checking SDRAM width */ 30 unsigned char min_delay; /* 15 for Back to Back Random Address */ 31 unsigned char burstl; /* 16 Burst Lengths Supported */ 32 unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ 33 unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 34 unsigned char cs_lat; /* 19 CS# Latency */ 35 unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ 36 unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 37 unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 38 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ 39 unsigned char clk_access2; /* 24 SDRAM Access from 40 Clk @ CL=X-0.5 (tAC) */ 41 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ 42 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ 43 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 44 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 45 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 46 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 47 unsigned char bank_dens; /* 31 Density of each bank on module */ 48 unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ 49 unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ 50 unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ 51 unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ 52 unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ 53 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 54 unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 55 unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 56 unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ 57 unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ 58 unsigned char res_46; /* 46 Reserved */ 59 unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ 60 unsigned char res_48_61[14]; /* 48-61 Reserved */ 61 unsigned char spd_rev; /* 62 SPD Data Revision Code */ 62 unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 63 unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ 64 unsigned char mloc; /* 72 Manufacturing Location */ 65 unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 66 unsigned char rev[2]; /* 91 Revision Code */ 67 unsigned char mdate[2]; /* 93 Manufacturing Date */ 68 unsigned char sernum[4]; /* 95 Assembly Serial Number */ 69 unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ 70 71 } ddr1_spd_eeprom_t; 72 73 /* 74 * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", 75 * SPD Revision 1.2 76 */ 77 typedef struct ddr2_spd_eeprom_s { 78 unsigned char info_size; /* 0 # bytes written into serial memory */ 79 unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 80 unsigned char mem_type; /* 2 Fundamental memory type */ 81 unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 82 unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 83 unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ 84 unsigned char dataw; /* 6 Module Data Width */ 85 unsigned char res_7; /* 7 Reserved */ 86 unsigned char voltage; /* 8 Voltage intf std of this assembly */ 87 unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 88 unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 89 unsigned char config; /* 11 DIMM Configuration type */ 90 unsigned char refresh; /* 12 Refresh Rate/Type */ 91 unsigned char primw; /* 13 Primary SDRAM Width */ 92 unsigned char ecw; /* 14 Error Checking SDRAM width */ 93 unsigned char res_15; /* 15 Reserved */ 94 unsigned char burstl; /* 16 Burst Lengths Supported */ 95 unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ 96 unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 97 unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ 98 unsigned char dimm_type; /* 20 DIMM type information */ 99 unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 100 unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 101 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ 102 unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ 103 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ 104 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ 105 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 106 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 107 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 108 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 109 unsigned char rank_dens; /* 31 Density of each rank on module */ 110 unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ 111 unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ 112 unsigned char data_setup; /* 34 Data Input Setup Time 113 Before Strobe (tDS) */ 114 unsigned char data_hold; /* 35 Data Input Hold Time 115 After Strobe (tDH) */ 116 unsigned char twr; /* 36 Write Recovery time tWR */ 117 unsigned char twtr; /* 37 Int write to read delay tWTR */ 118 unsigned char trtp; /* 38 Int read to precharge delay tRTP */ 119 unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ 120 unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ 121 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 122 unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 123 unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 124 unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ 125 unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ 126 unsigned char pll_relock; /* 46 PLL Relock time */ 127 unsigned char t_casemax; /* 47 Tcasemax */ 128 unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from 129 Top (Case) to Ambient (Psi T-A DRAM) */ 130 unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient 131 due to Activate-Precharge/Mode Bits 132 (DT0/Mode Bits) */ 133 unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient 134 due to Precharge/Quiet Standby 135 (DT2N/DT2Q) */ 136 unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient 137 due to Precharge Power-Down (DT2P) */ 138 unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient 139 due to Active Standby (DT3N) */ 140 unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient 141 due to Active Power-Down with 142 Fast PDN Exit (DT3Pfast) */ 143 unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient 144 due to Active Power-Down with Slow 145 PDN Exit (DT3Pslow) */ 146 unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient 147 due to Page Open Burst Read/DT4R4W 148 Mode Bit (DT4R/DT4R4W Mode Bit) */ 149 unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient 150 due to Burst Refresh (DT5B) */ 151 unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient 152 due to Bank Interleave Reads with 153 Auto-Precharge (DT7) */ 154 unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form 155 Top (Case) to Ambient (Psi T-A PLL) */ 156 unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package 157 from Top (Case) to Ambient 158 (Psi T-A Register) */ 159 unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient 160 due to PLL Active (DT PLL Active) */ 161 unsigned char dtregact; /* 61 Register Case Temperature Rise from 162 Ambient due to Register Active/Mode Bit 163 (DT Register Active/Mode Bit) */ 164 unsigned char spd_rev; /* 62 SPD Data Revision Code */ 165 unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 166 unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ 167 unsigned char mloc; /* 72 Manufacturing Location */ 168 unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 169 unsigned char rev[2]; /* 91 Revision Code */ 170 unsigned char mdate[2]; /* 93 Manufacturing Date */ 171 unsigned char sernum[4]; /* 95 Assembly Serial Number */ 172 unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ 173 174 } ddr2_spd_eeprom_t; 175 176 typedef struct ddr3_spd_eeprom_s { 177 /* General Section: Bytes 0-59 */ 178 unsigned char info_size_crc; /* 0 # bytes written into serial memory, 179 CRC coverage */ 180 unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ 181 unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ 182 unsigned char module_type; /* 3 Key Byte / Module Type */ 183 unsigned char density_banks; /* 4 SDRAM Density and Banks */ 184 unsigned char addressing; /* 5 SDRAM Addressing */ 185 unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ 186 unsigned char organization; /* 7 Module Organization */ 187 unsigned char bus_width; /* 8 Module Memory Bus Width */ 188 unsigned char ftb_div; /* 9 Fine Timebase (FTB) 189 Dividend / Divisor */ 190 unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ 191 unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ 192 unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ 193 unsigned char res_13; /* 13 Reserved */ 194 unsigned char caslat_lsb; /* 14 CAS Latencies Supported, 195 Least Significant Byte */ 196 unsigned char caslat_msb; /* 15 CAS Latencies Supported, 197 Most Significant Byte */ 198 unsigned char taa_min; /* 16 Min CAS Latency Time */ 199 unsigned char twr_min; /* 17 Min Write REcovery Time */ 200 unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ 201 unsigned char trrd_min; /* 19 Min Row Active to 202 Row Active Delay Time */ 203 unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ 204 unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ 205 unsigned char tras_min_lsb; /* 22 Min Active to Precharge 206 Delay Time */ 207 unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh 208 Delay Time, LSB */ 209 unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ 210 unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ 211 unsigned char twtr_min; /* 26 Min Internal Write to 212 Read Command Delay Time */ 213 unsigned char trtp_min; /* 27 Min Internal Read to Precharge 214 Command Delay Time */ 215 unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ 216 unsigned char tfaw_min; /* 29 Min Four Activate Window 217 Delay Time*/ 218 unsigned char opt_features; /* 30 SDRAM Optional Features */ 219 unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ 220 unsigned char therm_sensor; /* 32 Module Thermal Sensor */ 221 unsigned char device_type; /* 33 SDRAM device type */ 222 int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ 223 int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ 224 int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ 225 int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ 226 int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ 227 unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ 228 229 /* Module-Specific Section: Bytes 60-116 */ 230 union { 231 struct { 232 /* 60 (Unbuffered) Module Nominal Height */ 233 unsigned char mod_height; 234 /* 61 (Unbuffered) Module Maximum Thickness */ 235 unsigned char mod_thickness; 236 /* 62 (Unbuffered) Reference Raw Card Used */ 237 unsigned char ref_raw_card; 238 /* 63 (Unbuffered) Address Mapping from 239 Edge Connector to DRAM */ 240 unsigned char addr_mapping; 241 /* 64-116 (Unbuffered) Reserved */ 242 unsigned char res_64_116[53]; 243 } unbuffered; 244 struct { 245 /* 60 (Registered) Module Nominal Height */ 246 unsigned char mod_height; 247 /* 61 (Registered) Module Maximum Thickness */ 248 unsigned char mod_thickness; 249 /* 62 (Registered) Reference Raw Card Used */ 250 unsigned char ref_raw_card; 251 /* 63 DIMM Module Attributes */ 252 unsigned char modu_attr; 253 /* 64 RDIMM Thermal Heat Spreader Solution */ 254 unsigned char thermal; 255 /* 65 Register Manufacturer ID Code, Least Significant Byte */ 256 unsigned char reg_id_lo; 257 /* 66 Register Manufacturer ID Code, Most Significant Byte */ 258 unsigned char reg_id_hi; 259 /* 67 Register Revision Number */ 260 unsigned char reg_rev; 261 /* 68 Register Type */ 262 unsigned char reg_type; 263 /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ 264 unsigned char rcw[8]; 265 } registered; 266 unsigned char uc[57]; /* 60-116 Module-Specific Section */ 267 } mod_section; 268 269 /* Unique Module ID: Bytes 117-125 */ 270 unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ 271 unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ 272 unsigned char mloc; /* 119 Mfg Location */ 273 unsigned char mdate[2]; /* 120-121 Mfg Date */ 274 unsigned char sernum[4]; /* 122-125 Module Serial Number */ 275 276 /* CRC: Bytes 126-127 */ 277 unsigned char crc[2]; /* 126-127 SPD CRC */ 278 279 /* Other Manufacturer Fields and User Space: Bytes 128-255 */ 280 unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ 281 unsigned char mrev[2]; /* 146-147 Module Revision Code */ 282 283 unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ 284 unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ 285 286 unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ 287 unsigned char cust[80]; /* 176-255 Open for Customer Use */ 288 289 } ddr3_spd_eeprom_t; 290 291 /* From JEEC Standard No. 21-C release 23A */ 292 struct ddr4_spd_eeprom_s { 293 /* General Section: Bytes 0-127 */ 294 uint8_t info_size_crc; /* 0 # bytes */ 295 uint8_t spd_rev; /* 1 Total # bytes of SPD */ 296 uint8_t mem_type; /* 2 Key Byte / mem type */ 297 uint8_t module_type; /* 3 Key Byte / Module Type */ 298 uint8_t density_banks; /* 4 Density and Banks */ 299 uint8_t addressing; /* 5 Addressing */ 300 uint8_t package_type; /* 6 Package type */ 301 uint8_t opt_feature; /* 7 Optional features */ 302 uint8_t thermal_ref; /* 8 Thermal and refresh */ 303 uint8_t oth_opt_features; /* 9 Other optional features */ 304 uint8_t res_10; /* 10 Reserved */ 305 uint8_t module_vdd; /* 11 Module nominal voltage */ 306 uint8_t organization; /* 12 Module Organization */ 307 uint8_t bus_width; /* 13 Module Memory Bus Width */ 308 uint8_t therm_sensor; /* 14 Module Thermal Sensor */ 309 uint8_t ext_type; /* 15 Extended module type */ 310 uint8_t res_16; 311 uint8_t timebases; /* 17 MTb and FTB */ 312 uint8_t tck_min; /* 18 tCKAVGmin */ 313 uint8_t tck_max; /* 19 TCKAVGmax */ 314 uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ 315 uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ 316 uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ 317 uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ 318 uint8_t taa_min; /* 24 Min CAS Latency Time */ 319 uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ 320 uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ 321 uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ 322 uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ 323 uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ 324 uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ 325 uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ 326 uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ 327 uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ 328 uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ 329 uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ 330 uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ 331 uint8_t tfaw_min; /* 37 tFAW, lsb */ 332 uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ 333 uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ 334 uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ 335 uint8_t res_41[60-41]; /* 41 Rserved */ 336 uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ 337 uint8_t res_78[117-78]; /* 78~116, Reserved */ 338 int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ 339 int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ 340 int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ 341 int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ 342 int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ 343 int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ 344 int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ 345 int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ 346 int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ 347 /* CRC: Bytes 126-127 */ 348 uint8_t crc[2]; /* 126-127 SPD CRC */ 349 350 /* Module-Specific Section: Bytes 128-255 */ 351 union { 352 struct { 353 /* 128 (Unbuffered) Module Nominal Height */ 354 uint8_t mod_height; 355 /* 129 (Unbuffered) Module Maximum Thickness */ 356 uint8_t mod_thickness; 357 /* 130 (Unbuffered) Reference Raw Card Used */ 358 uint8_t ref_raw_card; 359 /* 131 (Unbuffered) Address Mapping from 360 Edge Connector to DRAM */ 361 uint8_t addr_mapping; 362 /* 132~253 (Unbuffered) Reserved */ 363 uint8_t res_132[254-132]; 364 /* 254~255 CRC */ 365 uint8_t crc[2]; 366 } unbuffered; 367 struct { 368 /* 128 (Registered) Module Nominal Height */ 369 uint8_t mod_height; 370 /* 129 (Registered) Module Maximum Thickness */ 371 uint8_t mod_thickness; 372 /* 130 (Registered) Reference Raw Card Used */ 373 uint8_t ref_raw_card; 374 /* 131 DIMM Module Attributes */ 375 uint8_t modu_attr; 376 /* 132 RDIMM Thermal Heat Spreader Solution */ 377 uint8_t thermal; 378 /* 133 Register Manufacturer ID Code, LSB */ 379 uint8_t reg_id_lo; 380 /* 134 Register Manufacturer ID Code, MSB */ 381 uint8_t reg_id_hi; 382 /* 135 Register Revision Number */ 383 uint8_t reg_rev; 384 /* 136 Address mapping from register to DRAM */ 385 uint8_t reg_map; 386 /* 137~253 Reserved */ 387 uint8_t res_137[254-137]; 388 /* 254~255 CRC */ 389 uint8_t crc[2]; 390 } registered; 391 struct { 392 /* 128 (Loadreduced) Module Nominal Height */ 393 uint8_t mod_height; 394 /* 129 (Loadreduced) Module Maximum Thickness */ 395 uint8_t mod_thickness; 396 /* 130 (Loadreduced) Reference Raw Card Used */ 397 uint8_t ref_raw_card; 398 /* 131 DIMM Module Attributes */ 399 uint8_t modu_attr; 400 /* 132 RDIMM Thermal Heat Spreader Solution */ 401 uint8_t thermal; 402 /* 133 Register Manufacturer ID Code, LSB */ 403 uint8_t reg_id_lo; 404 /* 134 Register Manufacturer ID Code, MSB */ 405 uint8_t reg_id_hi; 406 /* 135 Register Revision Number */ 407 uint8_t reg_rev; 408 /* 136 Address mapping from register to DRAM */ 409 uint8_t reg_map; 410 /* 137 Register Output Drive Strength for CMD/Add*/ 411 uint8_t reg_drv; 412 /* 138 Register Output Drive Strength for CK */ 413 uint8_t reg_drv_ck; 414 /* 139 Data Buffer Revision Number */ 415 uint8_t data_buf_rev; 416 /* 140 DRAM VrefDQ for Package Rank 0 */ 417 uint8_t vrefqe_r0; 418 /* 141 DRAM VrefDQ for Package Rank 1 */ 419 uint8_t vrefqe_r1; 420 /* 142 DRAM VrefDQ for Package Rank 2 */ 421 uint8_t vrefqe_r2; 422 /* 143 DRAM VrefDQ for Package Rank 3 */ 423 uint8_t vrefqe_r3; 424 /* 144 Data Buffer VrefDQ for DRAM Interface */ 425 uint8_t data_intf; 426 /* 427 * 145 Data Buffer MDQ Drive Strength and RTT 428 * for data rate <= 1866 429 */ 430 uint8_t data_drv_1866; 431 /* 432 * 146 Data Buffer MDQ Drive Strength and RTT 433 * for 1866 < data rate <= 2400 434 */ 435 uint8_t data_drv_2400; 436 /* 437 * 147 Data Buffer MDQ Drive Strength and RTT 438 * for 2400 < data rate <= 3200 439 */ 440 uint8_t data_drv_3200; 441 /* 148 DRAM Drive Strength */ 442 uint8_t dram_drv; 443 /* 444 * 149 DRAM ODT (RTT_WR, RTT_NOM) 445 * for data rate <= 1866 446 */ 447 uint8_t dram_odt_1866; 448 /* 449 * 150 DRAM ODT (RTT_WR, RTT_NOM) 450 * for 1866 < data rate <= 2400 451 */ 452 uint8_t dram_odt_2400; 453 /* 454 * 151 DRAM ODT (RTT_WR, RTT_NOM) 455 * for 2400 < data rate <= 3200 456 */ 457 uint8_t dram_odt_3200; 458 /* 459 * 152 DRAM ODT (RTT_PARK) 460 * for data rate <= 1866 461 */ 462 uint8_t dram_odt_park_1866; 463 /* 464 * 153 DRAM ODT (RTT_PARK) 465 * for 1866 < data rate <= 2400 466 */ 467 uint8_t dram_odt_park_2400; 468 /* 469 * 154 DRAM ODT (RTT_PARK) 470 * for 2400 < data rate <= 3200 471 */ 472 uint8_t dram_odt_park_3200; 473 uint8_t res_155[254-155]; /* Reserved */ 474 /* 254~255 CRC */ 475 uint8_t crc[2]; 476 } loadreduced; 477 uint8_t uc[128]; /* 128-255 Module-Specific Section */ 478 } mod_section; 479 480 uint8_t res_256[320-256]; /* 256~319 Reserved */ 481 482 /* Module supplier's data: Byte 320~383 */ 483 uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ 484 uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ 485 uint8_t mloc; /* 322 Mfg Location */ 486 uint8_t mdate[2]; /* 323~324 Mfg Date */ 487 uint8_t sernum[4]; /* 325~328 Module Serial Number */ 488 uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ 489 uint8_t mrev; /* 349 Module Revision Code */ 490 uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ 491 uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ 492 uint8_t stepping; /* 352 DRAM stepping */ 493 uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ 494 uint8_t res_382[2]; /* 382~383 Reserved */ 495 496 uint8_t user[512-384]; /* 384~511 End User Programmable */ 497 }; 498 499 extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); 500 extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); 501 extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); 502 extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); 503 extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); 504 unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); 505 506 /* 507 * Byte 2 Fundamental Memory Types. 508 */ 509 #define SPD_MEMTYPE_FPM (0x01) 510 #define SPD_MEMTYPE_EDO (0x02) 511 #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) 512 #define SPD_MEMTYPE_SDRAM (0x04) 513 #define SPD_MEMTYPE_ROM (0x05) 514 #define SPD_MEMTYPE_SGRAM (0x06) 515 #define SPD_MEMTYPE_DDR (0x07) 516 #define SPD_MEMTYPE_DDR2 (0x08) 517 #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) 518 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) 519 #define SPD_MEMTYPE_DDR3 (0x0B) 520 #define SPD_MEMTYPE_DDR4 (0x0C) 521 522 /* DIMM Type for DDR2 SPD (according to v1.3) */ 523 #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) 524 #define DDR2_SPD_DIMMTYPE_RDIMM (0x01) 525 #define DDR2_SPD_DIMMTYPE_UDIMM (0x02) 526 #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) 527 #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) 528 #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) 529 #define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) 530 #define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) 531 #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) 532 533 /* Byte 3 Key Byte / Module Type for DDR3 SPD */ 534 #define DDR3_SPD_MODULETYPE_MASK (0x0f) 535 #define DDR3_SPD_MODULETYPE_RDIMM (0x01) 536 #define DDR3_SPD_MODULETYPE_UDIMM (0x02) 537 #define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) 538 #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) 539 #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) 540 #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) 541 #define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) 542 #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) 543 #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) 544 #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) 545 #define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) 546 #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) 547 #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) 548 549 /* DIMM Type for DDR4 SPD */ 550 #define DDR4_SPD_MODULETYPE_MASK (0x0f) 551 #define DDR4_SPD_MODULETYPE_EXT (0x00) 552 #define DDR4_SPD_MODULETYPE_RDIMM (0x01) 553 #define DDR4_SPD_MODULETYPE_UDIMM (0x02) 554 #define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) 555 #define DDR4_SPD_MODULETYPE_LRDIMM (0x04) 556 #define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) 557 #define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) 558 #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) 559 #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) 560 #define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) 561 #define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) 562 563 #endif /* _DDR_SPD_H_ */ 564