1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Cortina PHY drivers 4 * 5 * Copyright 2014 Freescale Semiconductor, Inc. 6 */ 7 8 #ifndef _CORTINA_H_ 9 #define _CORTINA_H_ 10 11 #define VILLA_GLOBAL_CHIP_ID_LSB 0x000 12 #define VILLA_GLOBAL_CHIP_ID_MSB 0x001 13 #define VILLA_GLOBAL_BIST_CONTROL 0x002 14 #define VILLA_GLOBAL_BIST_STATUS 0x003 15 #define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 16 #define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 17 #define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A 18 #define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B 19 #define VILLA_GLOBAL_MSEQCLKCTRL 0x00E 20 #define VILLA_MSEQ_OPTIONS 0x1D0 21 #define VILLA_MSEQ_PC 0x1D3 22 #define VILLA_MSEQ_BANKSELECT 0x1DF 23 #define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB 24 #define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E 25 #define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403 26 #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404 27 #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405 28 #define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369 29 #define VILLA_MSEQ_ENABLE_MSB 0x194 30 #define VILLA_MSEQ_SPARE21_LSB 0x226 31 #define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0 32 #define VILLA_MSEQ_SPARE12_MSB 0x215 33 #define VILLA_MSEQ_SPARE2_LSB 0x200 34 #define VILLA_MSEQ_SPARE7_LSB 0x20A 35 #define VILLA_MSEQ_SPARE9_LSB 0x20E 36 #define VILLA_MSEQ_SPARE3_LSB 0x202 37 #define VILLA_MSEQ_SPARE3_MSB 0x203 38 #define VILLA_MSEQ_SPARE8_LSB 0x20C 39 #define VILLA_MSEQ_SPARE8_MSB 0x20D 40 #define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2 41 #define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4 42 #define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6 43 #define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8 44 #define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA 45 #define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC 46 #define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0 47 #define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE 48 #define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2 49 #define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2 50 #define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360 51 #define VILLA_MSEQ_POWER_DOWN_LSB 0x198 52 #define VILLA_MSEQ_POWER_DOWN_MSB 0x199 53 #define VILLA_MSEQ_CAL_RX_SLICER 0x1B8 54 #define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365 55 #define VILLA_MSEQ_COEF_INIT_SEL 0x1AE 56 #define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A 57 #define VILLA_MSEQ_SERDES_PARAM_LSB 0x195 58 #define VILLA_MSEQ_SPARE25_LSB 0x22E 59 #define VILLA_MSEQ_SPARE23_LSB 0x22A 60 #define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA 61 #define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030 62 #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812 63 #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813 64 #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 65 #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 66 67 /* Cortina CS4223 */ 68 #define CS4223_EEPROM_STATUS 0x5001 69 #define CS4223_EEPROM_FIRMWARE_LOADDONE 0x1 70 71 #define mseq_edc_bist_done (0x1<<0) 72 #define mseq_edc_bist_fail (0x1<<8) 73 74 struct cortina_reg_config { 75 unsigned short reg_addr; 76 unsigned short reg_value; 77 }; 78 #endif 79